drm/radeon: update rptr saving logic for memory buffers

[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen.c

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4b8e5c5fcf84931ba6288f7dcdd09111ab3f46d2..870009ad5f56d9a46e6eeebd010b15e9a9525025 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1364,17 +1364,25 @@ void evergreen_mc_program(struct radeon_device *rdev)
 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
        struct radeon_ring *ring = &rdev->ring[ib->ring];
+       u32 next_rptr;
 
        /* set to DX10/11 mode */
        radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
        radeon_ring_write(ring, 1);
 
        if (ring->rptr_save_reg) {
-               uint32_t next_rptr = ring->wptr + 3 + 4;
+               next_rptr = ring->wptr + 3 + 4;
                radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
                radeon_ring_write(ring, ((ring->rptr_save_reg - 
                                          PACKET3_SET_CONFIG_REG_START) >> 2));
                radeon_ring_write(ring, next_rptr);
+       } else if (rdev->wb.enabled) {
+               next_rptr = ring->wptr + 5 + 4;
+               radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
+               radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+               radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
+               radeon_ring_write(ring, next_rptr);
+               radeon_ring_write(ring, 0);
        }
 
        radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));