drm/i915/skl: Enabling PSR on Skylake

[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_psr.c

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 20db835493008d1e34cd6d33923957e8e7201693..b9f40c2e0af720ff3d8f18c4a53dcd187adb4eee 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
        struct drm_device *dev = dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
-       u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
-       u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
+       u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
+       u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
        uint32_t *data = (uint32_t *) vsc_psr;
        unsigned int i;
 
@@ -142,8 +142,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
        struct drm_device *dev = dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t aux_clock_divider;
+       uint32_t aux_data_reg, aux_ctl_reg;
        int precharge = 0x3;
-       bool only_standby = dev_priv->vbt.psr.full_link;
        static const uint8_t aux_msg[] = {
                [0] = DP_AUX_NATIVE_WRITE << 4,
                [1] = DP_SET_POWER >> 8,
@@ -157,27 +157,42 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
        aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
-       if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
-               only_standby = true;
-
        /* Enable PSR in sink */
-       if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
+       if (dev_priv->psr.link_standby)
                drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
                                   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
        else
                drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
                                   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
 
+       aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
+                               DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
+       aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
+                               DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
+
        /* Setup AUX registers */
        for (i = 0; i < sizeof(aux_msg); i += 4)
-               I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
+               I915_WRITE(aux_data_reg + i,
                           intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
-       I915_WRITE(EDP_PSR_AUX_CTL(dev),
+       if (INTEL_INFO(dev)->gen >= 9) {
+               uint32_t val;
+
+               val = I915_READ(aux_ctl_reg);
+               val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
+               val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
+               val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
+               val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+               /* Use hardcoded data values for PSR */
+               val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
+               I915_WRITE(aux_ctl_reg, val);
+       } else {
+               I915_WRITE(aux_ctl_reg,
                   DP_AUX_CH_CTL_TIME_OUT_400us |
                   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
                   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
                   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
+       }
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -226,12 +241,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
                               dev_priv->vbt.psr.idle_frames + 1 : 2;
        uint32_t val = 0x0;
        const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
-       bool only_standby = dev_priv->vbt.psr.full_link;
 
-       if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
-               only_standby = true;
-
-       if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
+       if (dev_priv->psr.link_standby) {
                val |= EDP_PSR_LINK_STANDBY;
                val |= EDP_PSR_TP2_TP3_TIME_0us;
                val |= EDP_PSR_TP1_TIME_0us;
@@ -271,14 +282,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
        }
 
        if (IS_HASWELL(dev) &&
-           I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
+           I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
                      S3D_ENABLE) {
                DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
                return false;
        }
 
        if (IS_HASWELL(dev) &&
-           intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+           intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
                return false;
        }
@@ -341,6 +352,13 @@ void intel_psr_enable(struct intel_dp *intel_dp)
        if (!intel_psr_match_conditions(intel_dp))
                goto unlock;
 
+       /* First we check VBT, but we must respect sink and source
+        * known restrictions */
+       dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
+       if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
+           (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
+               dev_priv->psr.link_standby = true;
+
        dev_priv->psr.busy_frontbuffer_bits = 0;
 
        if (HAS_DDI(dev)) {
@@ -352,6 +370,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 
                /* Enable PSR on the panel */
                hsw_psr_enable_sink(intel_dp);
+
+               if (INTEL_INFO(dev)->gen >= 9)
+                       intel_psr_activate(intel_dp);
        } else {
                vlv_psr_setup_vsc(intel_dp);