drm/i915: Store the BIT(engine->id) as the engine's mask

[linux-block.git] / drivers / gpu / drm / i915 / intel_lrc.c

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 578c8c98c718dbb60fb3d3ea2c4cfa33f0dced17..6ec6c4e175a23094544bc3d9909a78f4932f5159 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1777,7 +1777,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
        unsigned int i;
        int ret;
 
-       if (GEM_DEBUG_WARN_ON(engine->id != RCS))
+       if (GEM_DEBUG_WARN_ON(engine->id != RCS0))
                return -EINVAL;
 
        switch (INTEL_GEN(engine->i915)) {
@@ -2376,11 +2376,11 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
 
        if (INTEL_GEN(engine->i915) < 11) {
                const u8 irq_shifts[] = {
-                       [RCS]  = GEN8_RCS_IRQ_SHIFT,
-                       [BCS]  = GEN8_BCS_IRQ_SHIFT,
-                       [VCS]  = GEN8_VCS1_IRQ_SHIFT,
-                       [VCS2] = GEN8_VCS2_IRQ_SHIFT,
-                       [VECS] = GEN8_VECS_IRQ_SHIFT,
+                       [RCS0]  = GEN8_RCS_IRQ_SHIFT,
+                       [BCS0]  = GEN8_BCS_IRQ_SHIFT,
+                       [VCS0]  = GEN8_VCS0_IRQ_SHIFT,
+                       [VCS1]  = GEN8_VCS1_IRQ_SHIFT,
+                       [VECS0] = GEN8_VECS_IRQ_SHIFT,
                };
 
                shift = irq_shifts[engine->id];