Merge drm-next into drm-intel-next-queued (this time for real)

[linux-block.git] / drivers / gpu / drm / i915 / intel_drv.h

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 50874f4035cfe444f462c812e5aabf69016c36ca..652b11e788ccd79b8bb3039f66021e56e10d8034 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -935,6 +935,7 @@ struct intel_plane {
        enum plane_id id;
        enum pipe pipe;
        bool can_scale;
+       bool has_fbc;
        int max_downscale;
        uint32_t frontbuffer_bit;
 
@@ -1041,8 +1042,6 @@ struct intel_dp_compliance {
 
 struct intel_dp {
        i915_reg_t output_reg;
-       i915_reg_t aux_ch_ctl_reg;
-       i915_reg_t aux_ch_data_reg[5];
        uint32_t DP;
        int link_rate;
        uint8_t lane_count;
@@ -1052,6 +1051,7 @@ struct intel_dp {
        bool detect_done;
        bool channel_eq_status;
        bool reset_link_params;
+       enum aux_ch aux_ch;
        uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
        uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
        uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
@@ -1126,6 +1126,9 @@ struct intel_dp {
                                     int send_bytes,
                                     uint32_t aux_clock_divider);
 
+       i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
+       i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
+
        /* This is called before a link training is starterd */
        void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 
@@ -1508,6 +1511,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
 struct i915_vma *
 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
                           unsigned int rotation,
+                          bool uses_fence,
                           unsigned long *out_flags);
 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 struct drm_framebuffer *
@@ -1862,6 +1866,7 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
 
 /* intel_psr.c */
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable(struct intel_dp *intel_dp,
                      const struct intel_crtc_state *crtc_state);
 void intel_psr_disable(struct intel_dp *intel_dp,
@@ -1988,8 +1993,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
 void gen6_rps_busy(struct drm_i915_private *dev_priv);
 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
 void gen6_rps_idle(struct drm_i915_private *dev_priv);
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
-                   struct intel_rps_client *rps);
+void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
 void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);