/* Skylake supports following rates */
static const int gen9_rates[] = { 162000, 216000, 270000,
324000, 432000, 540000 };
+static const int chv_rates[] = { 162000, 202500, 210000, 216000,
+ 243000, 270000, 324000, 405000,
+ 420000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };
/**
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
-int
-intel_dp_max_link_bw(struct intel_dp *intel_dp)
+static int
+intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
- struct drm_device *dev = intel_dp->attached_connector->base.dev;
switch (max_link_bw) {
case DP_LINK_BW_1_62:
case DP_LINK_BW_2_7:
- break;
- case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
- if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
- /* WaDisableHBR2:skl */
- max_link_bw = DP_LINK_BW_2_7;
- else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
- INTEL_INFO(dev)->gen >= 8) &&
- intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
- max_link_bw = DP_LINK_BW_5_4;
- else
- max_link_bw = DP_LINK_BW_2_7;
+ case DP_LINK_BW_5_4:
break;
default:
WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
target_clock = fixed_mode->clock;
}
- max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
+ max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
}
static int
-intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
+intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- int i = 0;
- uint16_t val;
-
- if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
- /*
- * Receiver supports only main-link rate selection by
- * link rate table method, so read link rates from
- * supported_link_rates
- */
- for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
- val = le16_to_cpu(intel_dp->supported_rates[i]);
- if (val == 0)
- break;
+ if (intel_dp->num_supported_rates) {
+ *sink_rates = intel_dp->supported_rates;
+ return intel_dp->num_supported_rates;
+ }
- sink_rates[i] = val * 200;
- }
+ *sink_rates = default_rates;
- if (i <= 0)
- DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
- }
- return i;
+ return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
}
static int
-intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
+intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- int i;
- int max_default_rate;
-
- if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
- for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
- source_rates[i] = gen9_rates[i];
- } else {
- /* Index of the max_link_bw supported + 1 */
- max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
- for (i = 0; i < max_default_rate; ++i)
- source_rates[i] = default_rates[i];
+ if (INTEL_INFO(dev)->gen >= 9) {
+ *source_rates = gen9_rates;
+ return ARRAY_SIZE(gen9_rates);
+ } else if (IS_CHERRYVIEW(dev)) {
+ *source_rates = chv_rates;
+ return ARRAY_SIZE(chv_rates);
}
- return i;
+
+ *source_rates = default_rates;
+
+ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+ /* WaDisableHBR2:skl */
+ return (DP_LINK_BW_2_7 >> 3) + 1;
+ else if (INTEL_INFO(dev)->gen >= 8 ||
+ (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
+ return (DP_LINK_BW_5_4 >> 3) + 1;
+ else
+ return (DP_LINK_BW_2_7 >> 3) + 1;
}
static void
}
}
-static int intel_supported_rates(const int *source_rates, int source_len,
- const int *sink_rates, int sink_len,
- int *supported_rates)
+static int intersect_rates(const int *source_rates, int source_len,
+ const int *sink_rates, int sink_len,
+ int *supported_rates)
{
int i = 0, j = 0, k = 0;
- /* For panels with edp version less than 1.4 */
- if (sink_len == 0) {
- for (i = 0; i < source_len; ++i)
- supported_rates[i] = source_rates[i];
- return source_len;
- }
-
- /* For edp1.4 panels, find the common rates between source and sink */
while (i < source_len && j < sink_len) {
if (source_rates[i] == sink_rates[j]) {
+ if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
+ return k;
supported_rates[k] = source_rates[i];
++k;
++i;
return k;
}
+static int intel_supported_rates(struct intel_dp *intel_dp,
+ int *supported_rates)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ const int *source_rates, *sink_rates;
+ int source_len, sink_len;
+
+ sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+ source_len = intel_dp_source_rates(dev, &source_rates);
+
+ return intersect_rates(source_rates, source_len,
+ sink_rates, sink_len,
+ supported_rates);
+}
+
static int rate_to_index(int find, const int *rates)
{
int i = 0;
return i;
}
+int
+intel_dp_max_link_rate(struct intel_dp *intel_dp)
+{
+ int rates[DP_MAX_SUPPORTED_RATES] = {};
+ int len;
+
+ len = intel_supported_rates(intel_dp, rates);
+ if (WARN_ON(len <= 0))
+ return 162000;
+
+ return rates[rate_to_index(0, rates) - 1];
+}
+
+int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
+{
+ return rate_to_index(rate, intel_dp->supported_rates);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
int max_clock;
int bpp, mode_rate;
int link_avail, link_clock;
- int sink_rates[8];
- int supported_rates[8] = {0};
- int source_rates[8];
- int source_len, sink_len, supported_len;
+ int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
+ int supported_len;
- sink_len = intel_read_sink_rates(intel_dp, sink_rates);
-
- source_len = intel_read_source_rates(intel_dp, source_rates);
-
- supported_len = intel_supported_rates(source_rates, source_len,
- sink_rates, sink_len, supported_rates);
+ supported_len = intel_supported_rates(intel_dp, supported_rates);
/* No common link rates between source and sink */
WARN_ON(supported_len <= 0);
intel_dp->lane_count = lane_count;
- intel_dp->link_bw =
- drm_dp_link_rate_to_bw_code(supported_rates[clock]);
-
- if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
- intel_dp->rate_select =
- rate_to_index(supported_rates[clock], sink_rates);
+ if (intel_dp->num_supported_rates) {
intel_dp->link_bw = 0;
+ intel_dp->rate_select =
+ intel_dp_rate_select(intel_dp, supported_rates[clock]);
+ } else {
+ intel_dp->link_bw =
+ drm_dp_link_rate_to_bw_code(supported_rates[clock]);
+ intel_dp->rate_select = 0;
}
pipe_config->pipe_bpp = bpp;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
- if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])
+ if (intel_dp->num_supported_rates)
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
&intel_dp->rate_select, 1);
(intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
(rev >= 0x03)) { /* eDp v1.4 or higher */
+ __le16 supported_rates[DP_MAX_SUPPORTED_RATES];
+ int i;
+
intel_dp_dpcd_read_wake(&intel_dp->aux,
DP_SUPPORTED_LINK_RATES,
- intel_dp->supported_rates,
- sizeof(intel_dp->supported_rates));
+ supported_rates,
+ sizeof(supported_rates));
+
+ for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
+ int val = le16_to_cpu(supported_rates[i]);
+
+ if (val == 0)
+ break;
+
+ intel_dp->supported_rates[i] = val * 200;
+ }
+ intel_dp->num_supported_rates = i;
}
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_PRESENT))
projects / linux-2.6-block.git / blobdiff