drm/i915/skl: Restrict the ring frequency table programming to SKL

[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4bcbff9793d4383719a24d839511a6949175ef1a..00c60c1c5162eff6bab32df1ed4306efecdd53c3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1790,13 +1790,13 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);
 
-       I915_WRITE(DPLL(pipe), 0);
+       I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
        POSTING_READ(DPLL(pipe));
 }
 
 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-       u32 val = 0;
+       u32 val;
 
        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);
@@ -1805,8 +1805,9 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
         * Leave integrated clock source and reference clock enabled for pipe B.
         * The latter is needed for VGA hotplug / manual detection.
         */
+       val = DPLL_VGA_MODE_DIS;
        if (pipe == PIPE_B)
-               val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
+               val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
        I915_WRITE(DPLL(pipe), val);
        POSTING_READ(DPLL(pipe));
 
@@ -1821,7 +1822,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
        assert_pipe_disabled(dev_priv, pipe);
 
        /* Set PLL en = 0 */
-       val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
+       val = DPLL_SSC_REF_CLK_CHV |
+               DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
        if (pipe != PIPE_A)
                val |= DPLL_INTEGRATED_CRI_CLK_VLV;
        I915_WRITE(DPLL(pipe), val);
@@ -5047,6 +5049,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
                ironlake_fdi_pll_disable(intel_crtc);
        }
+
+       intel_crtc->active = false;
+       intel_update_watermarks(crtc);
 }
 
 static void haswell_crtc_disable(struct drm_crtc *crtc)
@@ -5092,6 +5097,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->post_disable)
                        encoder->post_disable(encoder);
+
+       intel_crtc->active = false;
+       intel_update_watermarks(crtc);
 }
 
 static void i9xx_pfit_enable(struct intel_crtc *crtc)
@@ -6156,6 +6164,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 
        if (!IS_GEN2(dev))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
+       intel_crtc->active = false;
+       intel_update_watermarks(crtc);
 }
 
 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
@@ -7222,8 +7233,8 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
         * clock for pipe B, since VGA hotplug / manual detection depends
         * on it.
         */
-       dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
-               DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+       dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
+               DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
        /* We should never disable this, set it here for state tracking */
        if (crtc->pipe == PIPE_B)
                dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
@@ -7329,8 +7340,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
 static void chv_compute_dpll(struct intel_crtc *crtc,
                             struct intel_crtc_state *pipe_config)
 {
-       pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
-               DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+       pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
+               DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
                DPLL_VCO_ENABLE;
        if (crtc->pipe != PIPE_A)
                pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
@@ -14385,9 +14396,27 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
        return drm_gem_handle_create(file, &obj->base, handle);
 }
 
+static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
+                                       struct drm_file *file,
+                                       unsigned flags, unsigned color,
+                                       struct drm_clip_rect *clips,
+                                       unsigned num_clips)
+{
+       struct drm_device *dev = fb->dev;
+       struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+       struct drm_i915_gem_object *obj = intel_fb->obj;
+
+       mutex_lock(&dev->struct_mutex);
+       intel_fb_obj_flush(obj, false, ORIGIN_GTT);
+       mutex_unlock(&dev->struct_mutex);
+
+       return 0;
+}
+
 static const struct drm_framebuffer_funcs intel_fb_funcs = {
        .destroy = intel_user_framebuffer_destroy,
        .create_handle = intel_user_framebuffer_create_handle,
+       .dirty = intel_user_framebuffer_dirty,
 };
 
 static