Merge tag 'rproc-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc...

[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_device_info.h

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e7d2cf7d65c85d04ecded3b283956c3e86af8b48..23bf230aa10486a931a355881d86ae58c7fcf6a2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -89,6 +89,7 @@ enum intel_platform {
        INTEL_XEHPSDV,
        INTEL_DG2,
        INTEL_PONTEVECCHIO,
+       INTEL_METEORLAKE,
        INTEL_MAX_PLATFORMS
 };
 
@@ -126,6 +127,10 @@ enum intel_platform {
  */
 #define INTEL_SUBPLATFORM_N    1
 
+/* MTL */
+#define INTEL_SUBPLATFORM_M    0
+#define INTEL_SUBPLATFORM_P    1
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@@ -143,6 +148,7 @@ enum intel_ppgtt_type {
        func(needs_compact_pt); \
        func(gpu_reset_clobbers_display); \
        func(has_reset_engine); \
+       func(has_3d_pipeline); \
        func(has_4tile); \
        func(has_flat_ccs); \
        func(has_global_mocs); \
@@ -150,11 +156,14 @@ enum intel_ppgtt_type {
        func(has_heci_pxp); \
        func(has_heci_gscfi); \
        func(has_guc_deprivilege); \
+       func(has_l3_ccs_read); \
        func(has_l3_dpf); \
        func(has_llc); \
        func(has_logical_ring_contexts); \
        func(has_logical_ring_elsq); \
-       func(has_mslices); \
+       func(has_media_ratio_mode); \
+       func(has_mslice_steering); \
+       func(has_one_eu_per_fuse_bit); \
        func(has_pooled_eu); \
        func(has_pxp); \
        func(has_rc6); \
@@ -210,8 +219,6 @@ struct intel_device_info {
 
        u32 memory_regions; /* regions supported by the HW */
 
-       u32 display_mmio_offset;
-
        u8 gt; /* GT number, 0 if undefined */
 
 #define DEFINE_FLAG(name) u8 name:1
@@ -227,27 +234,30 @@ struct intel_device_info {
                u8 fbc_mask;
                u8 abox_mask;
 
+               struct {
+                       u16 size; /* in blocks */
+                       u8 slice_mask;
+               } dbuf;
+
 #define DEFINE_FLAG(name) u8 name:1
                DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
-       } display;
 
-       struct {
-               u16 size; /* in blocks */
-               u8 slice_mask;
-       } dbuf;
-
-       /* Register offsets for the various display pipes and transcoders */
-       int pipe_offsets[I915_MAX_TRANSCODERS];
-       int trans_offsets[I915_MAX_TRANSCODERS];
-       int cursor_offsets[I915_MAX_PIPES];
-
-       struct color_luts {
-               u32 degamma_lut_size;
-               u32 gamma_lut_size;
-               u32 degamma_lut_tests;
-               u32 gamma_lut_tests;
-       } color;
+               /* Global register offset for the display engine */
+               u32 mmio_offset;
+
+               /* Register offsets for the various display pipes and transcoders */
+               u32 pipe_offsets[I915_MAX_TRANSCODERS];
+               u32 trans_offsets[I915_MAX_TRANSCODERS];
+               u32 cursor_offsets[I915_MAX_PIPES];
+
+               struct {
+                       u32 degamma_lut_size;
+                       u32 gamma_lut_size;
+                       u32 degamma_lut_tests;
+                       u32 gamma_lut_tests;
+               } color;
+       } display;
 };
 
 struct intel_runtime_info {