drm/i915: add intel_ddi_set_pipe_settings

[linux-block.git] / drivers / gpu / drm / i915 / intel_ddi.c

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9659c227dcf4c4e77f0866d3a5f34247a953d41e..e58df7176f9dc1548e0a15186df6a4f5ee312d14 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -827,6 +827,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
        return true;
 }
 
+void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
+{
+       struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+       enum pipe pipe = intel_crtc->pipe;
+       int type = intel_encoder->type;
+       uint32_t temp;
+
+       if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+
+               temp = PIPE_MSA_SYNC_CLK;
+               switch (intel_crtc->bpp) {
+               case 18:
+                       temp |= PIPE_MSA_6_BPC;
+                       break;
+               case 24:
+                       temp |= PIPE_MSA_8_BPC;
+                       break;
+               case 30:
+                       temp |= PIPE_MSA_10_BPC;
+                       break;
+               case 36:
+                       temp |= PIPE_MSA_12_BPC;
+                       break;
+               default:
+                       temp |= PIPE_MSA_8_BPC;
+                       WARN(1, "%d bpp unsupported by pipe DDI function\n",
+                            intel_crtc->bpp);
+               }
+               I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+       }
+}
+
 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 {
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);