Merge drm/drm-next into drm-intel-gt-next

[linux-block.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c32420cb8ed59030ad5e5c0c371854ab47c58f62..a19504ac86b14553fa830ec33ab7814601cf2fb5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -511,6 +511,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   TAG_BLOCK_CLKGATE_DIS                REG_BIT(7)
 
 #define GEN12_MERT_MOD_CTRL            _MMIO(0xcf28)
+#define RENDER_MOD_CTRL                        _MMIO(0xcf2c)
+#define COMP_MOD_CTRL                  _MMIO(0xcf30)
+#define VDBX_MOD_CTRL                  _MMIO(0xcf34)
+#define VEBX_MOD_CTRL                  _MMIO(0xcf38)
 #define   FORCE_MISS_FTLB              REG_BIT(3)
 
 #define GAB_CTL                                _MMIO(0x24000)
@@ -2684,7 +2688,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   RING_WAIT            (1 << 11) /* gen3+, PRBx_CTL */
 #define   RING_WAIT_SEMAPHORE  (1 << 10) /* gen6+ */
 
-#define GUCPMTIMESTAMP          _MMIO(0xC3E8)
+#define MISC_STATUS0           _MMIO(0xA500)
+#define MISC_STATUS1           _MMIO(0xA504)
 
 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
 #define GEN8_RING_CS_GPR(base, n)      _MMIO((base) + 0x600 + (n) * 8)
@@ -9768,6 +9773,7 @@ enum {
 
 #define GEN9_ROW_CHICKEN4                              _MMIO(0xe48c)
 #define   GEN12_DISABLE_GRF_CLEAR                      REG_BIT(13)
+#define   XEHP_DIS_BBL_SYSPIPE                         REG_BIT(11)
 #define   GEN12_DISABLE_TDL_PUSH                       REG_BIT(9)
 #define   GEN11_DIS_PICK_2ND_EU                                REG_BIT(7)
 #define   GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX      REG_BIT(4)