Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/drm-intel...

[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b5608237c226ee979338343ecdd9d175115..1412abcb27d422e9f34d609d6affc468ea74019b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1906,6 +1906,11 @@ enum i915_power_well_id {
 #define   CL_POWER_DOWN_ENABLE         (1 << 4)
 #define   SUS_CLOCK_CONFIG             (3 << 0)
 
+#define _ICL_PORT_CL_DW5_A     0x162014
+#define _ICL_PORT_CL_DW5_B     0x6C014
+#define ICL_PORT_CL_DW5(port)  _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
+                                                _ICL_PORT_CL_DW5_B)
+
 #define _PORT_CL1CM_DW9_A              0x162024
 #define _PORT_CL1CM_DW9_BC             0x6C024
 #define   IREF0RC_OFFSET_SHIFT         8
@@ -2029,7 +2034,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW5_LN0_AE                0x162454
 #define _CNL_PORT_TX_DW5_LN0_B         0x162654
 #define _CNL_PORT_TX_DW5_LN0_C         0x162C54
-#define _CNL_PORT_TX_DW5_LN0_D         0x162ED4
+#define _CNL_PORT_TX_DW5_LN0_D         0x162E54
 #define _CNL_PORT_TX_DW5_LN0_F         0x162854
 #define CNL_PORT_TX_DW5_GRP(port)      _MMIO_PORT6(port, \
                                                    _CNL_PORT_TX_DW5_GRP_AE, \
@@ -2060,7 +2065,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW7_LN0_AE                0x16245C
 #define _CNL_PORT_TX_DW7_LN0_B         0x16265C
 #define _CNL_PORT_TX_DW7_LN0_C         0x162C5C
-#define _CNL_PORT_TX_DW7_LN0_D         0x162EDC
+#define _CNL_PORT_TX_DW7_LN0_D         0x162E5C
 #define _CNL_PORT_TX_DW7_LN0_F         0x16285C
 #define CNL_PORT_TX_DW7_GRP(port)      _MMIO_PORT6(port, \
                                                    _CNL_PORT_TX_DW7_GRP_AE, \
@@ -2104,6 +2109,28 @@ enum i915_power_well_id {
 #define CNL_PORT_COMP_DW9              _MMIO(0x162124)
 #define CNL_PORT_COMP_DW10             _MMIO(0x162128)
 
+#define _ICL_PORT_COMP_DW0_A           0x162100
+#define _ICL_PORT_COMP_DW0_B           0x6C100
+#define ICL_PORT_COMP_DW0(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
+                                                        _ICL_PORT_COMP_DW0_B)
+#define _ICL_PORT_COMP_DW1_A           0x162104
+#define _ICL_PORT_COMP_DW1_B           0x6C104
+#define ICL_PORT_COMP_DW1(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
+                                                        _ICL_PORT_COMP_DW1_B)
+#define _ICL_PORT_COMP_DW3_A           0x16210C
+#define _ICL_PORT_COMP_DW3_B           0x6C10C
+#define ICL_PORT_COMP_DW3(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
+                                                        _ICL_PORT_COMP_DW3_B)
+#define _ICL_PORT_COMP_DW9_A           0x162124
+#define _ICL_PORT_COMP_DW9_B           0x6C124
+#define ICL_PORT_COMP_DW9(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
+                                                        _ICL_PORT_COMP_DW9_B)
+#define _ICL_PORT_COMP_DW10_A          0x162128
+#define _ICL_PORT_COMP_DW10_B          0x6C128
+#define ICL_PORT_COMP_DW10(port)       _MMIO_PORT(port, \
+                                                  _ICL_PORT_COMP_DW10_A, \
+                                                  _ICL_PORT_COMP_DW10_B)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A                        0x16218C
 #define _PORT_REF_DW3_BC               0x6C18C
@@ -7138,6 +7165,8 @@ enum {
 #define  DISP_DATA_PARTITION_5_6       (1<<6)
 #define  DISP_IPC_ENABLE               (1<<3)
 #define DBUF_CTL       _MMIO(0x45008)
+#define DBUF_CTL_S1    _MMIO(0x45008)
+#define DBUF_CTL_S2    _MMIO(0x44FE8)
 #define  DBUF_POWER_REQUEST            (1<<31)
 #define  DBUF_POWER_STATE              (1<<30)
 #define GEN7_MSG_CTL   _MMIO(0x45010)
@@ -7147,8 +7176,9 @@ enum {
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1<<4)
 
 #define GEN8_CHICKEN_DCPR_1            _MMIO(0x46430)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
-#define   MASK_WAKEMEM                 (1<<13)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
+#define   MASK_WAKEMEM                 (1 << 13)
+#define   CNL_DDI_CLOCK_REG_ACCESS_ON  (1 << 7)
 
 #define SKL_DFSM                       _MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK      (3 << 23)
@@ -7160,8 +7190,12 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE                (1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE                (1 << 28)
 
-#define SKL_DSSM                       _MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz        (1 << 31)
+#define SKL_DSSM                               _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz                (1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK         (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz                (0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz      (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz      (2 << 29)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1      _MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL        (1<<14)
@@ -8794,20 +8828,21 @@ enum skl_power_gate {
 
 /* CDCLK_CTL */
 #define CDCLK_CTL                      _MMIO(0x46000)
-#define  CDCLK_FREQ_SEL_MASK           (3<<26)
-#define  CDCLK_FREQ_450_432            (0<<26)
-#define  CDCLK_FREQ_540                        (1<<26)
-#define  CDCLK_FREQ_337_308            (2<<26)
-#define  CDCLK_FREQ_675_617            (3<<26)
-#define  BXT_CDCLK_CD2X_DIV_SEL_MASK   (3<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1      (0<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1_5    (1<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_2      (2<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_4      (3<<22)
-#define  BXT_CDCLK_CD2X_PIPE(pipe)     ((pipe)<<20)
-#define  CDCLK_DIVMUX_CD_OVERRIDE      (1<<19)
+#define  CDCLK_FREQ_SEL_MASK           (3 << 26)
+#define  CDCLK_FREQ_450_432            (0 << 26)
+#define  CDCLK_FREQ_540                        (1 << 26)
+#define  CDCLK_FREQ_337_308            (2 << 26)
+#define  CDCLK_FREQ_675_617            (3 << 26)
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK   (3 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1      (0 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5    (1 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2      (2 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4      (3 << 22)
+#define  BXT_CDCLK_CD2X_PIPE(pipe)     ((pipe) << 20)
+#define  CDCLK_DIVMUX_CD_OVERRIDE      (1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE      BXT_CDCLK_CD2X_PIPE(3)
-#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE        (1<<16)
+#define  ICL_CDCLK_CD2X_PIPE_NONE      (7 << 19)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE        (1 << 16)
 #define  CDCLK_FREQ_DECIMAL_MASK       (0x7ff)
 
 /* LCPLL_CTL */
@@ -9716,4 +9751,10 @@ enum skl_power_gate {
 #define  MMCD_PCLA             (1 << 31)
 #define  MMCD_HOTSPOT_EN       (1 << 27)
 
+#define _ICL_PHY_MISC_A                0x64C00
+#define _ICL_PHY_MISC_B                0x64C04
+#define ICL_PHY_MISC(port)     _MMIO_PORT(port, _ICL_PHY_MISC_A, \
+                                                _ICL_PHY_MISC_B)
+#define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN      (1 << 23)
+
 #endif /* _I915_REG_H_ */