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Merge tag 'x86-urgent-2022-08-06' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_pci.c
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index acf688b698c396e760160c43e714898fa28e21d8..aacc10f2e73f45e715134b211035379306349f78 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -38,43 +38,43 @@
        .display.ver = (x)
 
 #define I845_PIPE_OFFSETS \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
        }
 
 #define I9XX_PIPE_OFFSETS \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
        }
 
 #define IVB_PIPE_OFFSETS \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
                [TRANSCODER_C] = PIPE_C_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
                [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
        }
 
 #define HSW_PIPE_OFFSETS \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
                [TRANSCODER_C] = PIPE_C_OFFSET, \
                [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
                [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -82,44 +82,44 @@
        }
 
 #define CHV_PIPE_OFFSETS \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
                [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
                [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
        }
 
 #define I845_CURSOR_OFFSETS \
-       .cursor_offsets = { \
+       .display.cursor_offsets = { \
                [PIPE_A] = CURSOR_A_OFFSET, \
        }
 
 #define I9XX_CURSOR_OFFSETS \
-       .cursor_offsets = { \
+       .display.cursor_offsets = { \
                [PIPE_A] = CURSOR_A_OFFSET, \
                [PIPE_B] = CURSOR_B_OFFSET, \
        }
 
 #define CHV_CURSOR_OFFSETS \
-       .cursor_offsets = { \
+       .display.cursor_offsets = { \
                [PIPE_A] = CURSOR_A_OFFSET, \
                [PIPE_B] = CURSOR_B_OFFSET, \
                [PIPE_C] = CHV_CURSOR_C_OFFSET, \
        }
 
 #define IVB_CURSOR_OFFSETS \
-       .cursor_offsets = { \
+       .display.cursor_offsets = { \
                [PIPE_A] = CURSOR_A_OFFSET, \
                [PIPE_B] = IVB_CURSOR_B_OFFSET, \
                [PIPE_C] = IVB_CURSOR_C_OFFSET, \
        }
 
 #define TGL_CURSOR_OFFSETS \
-       .cursor_offsets = { \
+       .display.cursor_offsets = { \
                [PIPE_A] = CURSOR_A_OFFSET, \
                [PIPE_B] = IVB_CURSOR_B_OFFSET, \
                [PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -127,30 +127,33 @@
        }
 
 #define I9XX_COLORS \
-       .color = { .gamma_lut_size = 256 }
+       .display.color = { .gamma_lut_size = 256 }
 #define I965_COLORS \
-       .color = { .gamma_lut_size = 129, \
+       .display.color = { .gamma_lut_size = 129, \
                   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
        }
 #define ILK_COLORS \
-       .color = { .gamma_lut_size = 1024 }
+       .display.color = { .gamma_lut_size = 1024 }
 #define IVB_COLORS \
-       .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+       .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 #define CHV_COLORS \
-       .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
-                  .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-                  .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+       .display.color = { \
+               .degamma_lut_size = 65, .gamma_lut_size = 257, \
+               .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+               .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
        }
 #define GLK_COLORS \
-       .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
-                  .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-                                       DRM_COLOR_LUT_EQUAL_CHANNELS, \
+       .display.color = { \
+               .degamma_lut_size = 33, .gamma_lut_size = 1024, \
+               .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+                                    DRM_COLOR_LUT_EQUAL_CHANNELS, \
        }
 #define ICL_COLORS \
-       .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
-                  .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-                                       DRM_COLOR_LUT_EQUAL_CHANNELS, \
-                  .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+       .display.color = { \
+               .degamma_lut_size = 33, .gamma_lut_size = 262145, \
+               .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+                                    DRM_COLOR_LUT_EQUAL_CHANNELS, \
+               .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
        }
 
 /* Keep in gen based order, and chronological order within a gen */
@@ -171,6 +174,7 @@
        .display.overlay_needs_physical = 1, \
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
+       .has_3d_pipeline = 1, \
        .hws_needs_physical = 1, \
        .unfenced_needs_alignment = 1, \
        .platform_engine_mask = BIT(RCS0), \
@@ -190,6 +194,7 @@
        .display.has_overlay = 1, \
        .display.overlay_needs_physical = 1, \
        .display.has_gmch = 1, \
+       .has_3d_pipeline = 1, \
        .gpu_reset_clobbers_display = true, \
        .hws_needs_physical = 1, \
        .unfenced_needs_alignment = 1, \
@@ -232,6 +237,7 @@ static const struct intel_device_info i865g_info = {
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
        .platform_engine_mask = BIT(RCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 32, \
@@ -323,6 +329,7 @@ static const struct intel_device_info pnv_m_info = {
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
        .platform_engine_mask = BIT(RCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 36, \
@@ -374,6 +381,7 @@ static const struct intel_device_info gm45_info = {
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        /* ilk does support rc6, but we do not implement [power] contexts */ \
@@ -405,6 +413,7 @@ static const struct intel_device_info ilk_m_info = {
        .display.has_hotplug = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+       .has_3d_pipeline = 1, \
        .has_coherent_ggtt = true, \
        .has_llc = 1, \
        .has_rc6 = 1, \
@@ -456,6 +465,7 @@ static const struct intel_device_info snb_m_gt2_info = {
        .display.has_hotplug = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+       .has_3d_pipeline = 1, \
        .has_coherent_ggtt = true, \
        .has_llc = 1, \
        .has_rc6 = 1, \
@@ -529,7 +539,7 @@ static const struct intel_device_info vlv_info = {
        .has_snoop = true,
        .has_coherent_ggtt = false,
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
-       .display_mmio_offset = VLV_DISPLAY_BASE,
+       .display.mmio_offset = VLV_DISPLAY_BASE,
        I9XX_PIPE_OFFSETS,
        I9XX_CURSOR_OFFSETS,
        I965_COLORS,
@@ -627,7 +637,7 @@ static const struct intel_device_info chv_info = {
        .has_reset_engine = 1,
        .has_snoop = true,
        .has_coherent_ggtt = false,
-       .display_mmio_offset = VLV_DISPLAY_BASE,
+       .display.mmio_offset = VLV_DISPLAY_BASE,
        CHV_PIPE_OFFSETS,
        CHV_CURSOR_OFFSETS,
        CHV_COLORS,
@@ -649,8 +659,8 @@ static const struct intel_device_info chv_info = {
        .display.has_ipc = 1, \
        .display.has_psr = 1, \
        .display.has_psr_hw_tracking = 1, \
-       .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-       .dbuf.slice_mask = BIT(DBUF_S1)
+       .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+       .display.dbuf.slice_mask = BIT(DBUF_S1)
 
 #define SKL_PLATFORM \
        GEN9_FEATURES, \
@@ -685,13 +695,14 @@ static const struct intel_device_info skl_gt4_info = {
 #define GEN9_LP_FEATURES \
        GEN(9), \
        .is_lp = 1, \
-       .dbuf.slice_mask = BIT(DBUF_S1), \
+       .display.dbuf.slice_mask = BIT(DBUF_S1), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
        .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
+       .has_3d_pipeline = 1, \
        .has_64bit_reloc = 1, \
        .display.has_ddi = 1, \
        .display.has_fpga_dbg = 1, \
@@ -722,14 +733,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
        GEN9_LP_FEATURES,
        PLATFORM(INTEL_BROXTON),
-       .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+       .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 };
 
 static const struct intel_device_info glk_info = {
        GEN9_LP_FEATURES,
        PLATFORM(INTEL_GEMINILAKE),
        .display.ver = 10,
-       .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+       .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
        GLK_COLORS,
 };
 
@@ -801,7 +812,7 @@ static const struct intel_device_info cml_gt2_info = {
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
                [TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -809,7 +820,7 @@ static const struct intel_device_info cml_gt2_info = {
                [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
                [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
                [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -819,8 +830,8 @@ static const struct intel_device_info cml_gt2_info = {
        }, \
        GEN(11), \
        ICL_COLORS, \
-       .dbuf.size = 2048, \
-       .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+       .display.dbuf.size = 2048, \
+       .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
        .display.has_dsc = 1, \
        .has_coherent_ggtt = false, \
        .has_logical_ring_elsq = 1
@@ -854,7 +865,7 @@ static const struct intel_device_info jsl_info = {
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-       .pipe_offsets = { \
+       .display.pipe_offsets = { \
                [TRANSCODER_A] = PIPE_A_OFFSET, \
                [TRANSCODER_B] = PIPE_B_OFFSET, \
                [TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -862,7 +873,7 @@ static const struct intel_device_info jsl_info = {
                [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
                [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
        }, \
-       .trans_offsets = { \
+       .display.trans_offsets = { \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
                [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -929,22 +940,15 @@ static const struct intel_device_info adl_s_info = {
        .dma_mask_size = 39,
 };
 
-#define XE_LPD_CURSOR_OFFSETS \
-       .cursor_offsets = { \
-               [PIPE_A] = CURSOR_A_OFFSET, \
-               [PIPE_B] = IVB_CURSOR_B_OFFSET, \
-               [PIPE_C] = IVB_CURSOR_C_OFFSET, \
-               [PIPE_D] = TGL_CURSOR_D_OFFSET, \
-       }
-
 #define XE_LPD_FEATURES \
        .display.abox_mask = GENMASK(1, 0),                                     \
-       .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,             \
-                  .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |          \
-                                       DRM_COLOR_LUT_EQUAL_CHANNELS,           \
+       .display.color = {                                                      \
+               .degamma_lut_size = 128, .gamma_lut_size = 1024,                \
+               .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
+                                    DRM_COLOR_LUT_EQUAL_CHANNELS,              \
        },                                                                      \
-       .dbuf.size = 4096,                                                      \
-       .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
+       .display.dbuf.size = 4096,                                              \
+       .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
                BIT(DBUF_S4),                                                   \
        .display.has_ddi = 1,                                                   \
        .display.has_dmc = 1,                                                   \
@@ -959,7 +963,7 @@ static const struct intel_device_info adl_s_info = {
        .display.has_psr = 1,                                                   \
        .display.ver = 13,                                                      \
        .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
-       .pipe_offsets = {                                                       \
+       .display.pipe_offsets = {                                               \
                [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
                [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
                [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
@@ -967,7 +971,7 @@ static const struct intel_device_info adl_s_info = {
                [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
                [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
        },                                                                      \
-       .trans_offsets = {                                                      \
+       .display.trans_offsets = {                                              \
                [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
                [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
                [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
@@ -975,7 +979,7 @@ static const struct intel_device_info adl_s_info = {
                [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
                [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
        },                                                                      \
-       XE_LPD_CURSOR_OFFSETS
+       TGL_CURSOR_OFFSETS
 
 static const struct intel_device_info adl_p_info = {
        GEN12_FEATURES,
@@ -1005,6 +1009,7 @@ static const struct intel_device_info adl_p_info = {
        .graphics.rel = 50, \
        XE_HP_PAGE_SIZES, \
        .dma_mask_size = 46, \
+       .has_3d_pipeline = 1, \
        .has_64bit_reloc = 1, \
        .has_flat_ccs = 1, \
        .has_global_mocs = 1, \
@@ -1012,7 +1017,7 @@ static const struct intel_device_info adl_p_info = {
        .has_llc = 1, \
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_elsq = 1, \
-       .has_mslices = 1, \
+       .has_mslice_steering = 1, \
        .has_rc6 = 1, \
        .has_reset_engine = 1, \
        .has_rps = 1, \
@@ -1033,6 +1038,7 @@ static const struct intel_device_info xehpsdv_info = {
        .display = { },
        .has_64k_pages = 1,
        .needs_compact_pt = 1,
+       .has_media_ratio_mode = 1,
        .platform_engine_mask =
                BIT(RCS0) | BIT(BCS0) |
                BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1054,6 +1060,7 @@ static const struct intel_device_info xehpsdv_info = {
        .has_guc_deprivilege = 1, \
        .has_heci_pxp = 1, \
        .needs_compact_pt = 1, \
+       .has_media_ratio_mode = 1, \
        .platform_engine_mask = \
                BIT(RCS0) | BIT(BCS0) | \
                BIT(VECS0) | BIT(VECS1) | \
@@ -1068,7 +1075,6 @@ static const struct intel_device_info dg2_info = {
        .require_force_probe = 1,
 };
 
-__maybe_unused
 static const struct intel_device_info ats_m_info = {
        DG2_FEATURES,
        .display = { 0 },
@@ -1077,7 +1083,12 @@ static const struct intel_device_info ats_m_info = {
 
 #define XE_HPC_FEATURES \
        XE_HP_FEATURES, \
-       .dma_mask_size = 52
+       .dma_mask_size = 52, \
+       .has_3d_pipeline = 0, \
+       .has_guc_deprivilege = 1, \
+       .has_l3_ccs_read = 1, \
+       .has_mslice_steering = 0, \
+       .has_one_eu_per_fuse_bit = 1
 
 __maybe_unused
 static const struct intel_device_info pvc_info = {
@@ -1096,6 +1107,31 @@ static const struct intel_device_info pvc_info = {
        .require_force_probe = 1,
 };
 
+#define XE_LPDP_FEATURES       \
+       XE_LPD_FEATURES,        \
+       .display.ver = 14,      \
+       .display.has_cdclk_crawl = 1
+
+__maybe_unused
+static const struct intel_device_info mtl_info = {
+       XE_HP_FEATURES,
+       XE_LPDP_FEATURES,
+       /*
+        * Real graphics IP version will be obtained from hardware GMD_ID
+        * register.  Value provided here is just for sanity checking.
+        */
+       .graphics.ver = 12,
+       .graphics.rel = 70,
+       .media.ver = 13,
+       PLATFORM(INTEL_METEORLAKE),
+       .display.has_modular_fia = 1,
+       .has_flat_ccs = 0,
+       .has_snoop = 1,
+       .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
+       .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
+       .require_force_probe = 1,
+};
+
 #undef PLATFORM
 
 /*
@@ -1177,6 +1213,8 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_RPLS_IDS(&adl_s_info),
        INTEL_RPLP_IDS(&adl_p_info),
        INTEL_DG2_IDS(&dg2_info),
+       INTEL_ATS_M_IDS(&ats_m_info),
+       INTEL_MTL_IDS(&mtl_info),
        {0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
Linux 6.x block layer and io_uring tree(s)