Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes

[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 30d6af6c09bbe33e2fc8a333252b838f1817488c..df278b2685bff16c4da8b1a26eb6982149fce4e1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -304,35 +304,39 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 
 
 /**
- * Returns the size of the fence for a tiled object of the given size.
+ * Returns whether an object is currently fenceable.  If not, it may need
+ * to be unbound and have its pitch adjusted.
  */
-static int
-i915_get_fence_size(struct drm_device *dev, int size)
+bool
+i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj)
 {
-       int i;
-       int start;
+       struct drm_i915_gem_object *obj_priv = obj->driver_private;
 
        if (IS_I965G(dev)) {
                /* The 965 can have fences at any page boundary. */
-               return ALIGN(size, 4096);
+               if (obj->size & 4095)
+                       return false;
+               return true;
+       } else if (IS_I9XX(dev)) {
+               if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
+                       return false;
        } else {
-               /* Align the size to a power of two greater than the smallest
-                * fence size.
-                */
-               if (IS_I9XX(dev))
-                       start = 1024 * 1024;
-               else
-                       start = 512 * 1024;
+               if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
+                       return false;
+       }
 
-               for (i = start; i < size; i <<= 1)
-                       ;
+       /* Power of two sized... */
+       if (obj->size & (obj->size - 1))
+               return false;
 
-               return i;
-       }
+       /* Objects must be size aligned as well */
+       if (obj_priv->gtt_offset & (obj->size - 1))
+               return false;
+       return true;
 }
 
 /* Check pitch constriants for all chips & tiling formats */
-static bool
+bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 {
        int tile_width;
@@ -384,12 +388,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
        if (stride & (stride - 1))
                return false;
 
-       /* We don't 0handle the aperture area covered by the fence being bigger
-        * than the object size.
-        */
-       if (i915_get_fence_size(dev, size) != size)
-               return false;
-
        return true;
 }