drm/i915: Set up an MTRR covering the GTT at driver load.

[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4756e5cd6b5e1142781c0dfe35b5f85aeb0df886..f471d218b89ad214f21fa578d71916ff6ce9f242 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -72,6 +72,18 @@ enum pipe {
 #define WATCH_INACTIVE 0
 #define WATCH_PWRITE   0
 
+#define I915_GEM_PHYS_CURSOR_0 1
+#define I915_GEM_PHYS_CURSOR_1 2
+#define I915_GEM_PHYS_OVERLAY_REGS 3
+#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
+
+struct drm_i915_gem_phys_object {
+       int id;
+       struct page **page_list;
+       drm_dma_handle_t *handle;
+       struct drm_gem_object *cur_obj;
+};
+
 typedef struct _drm_i915_ring_buffer {
        int tail_mask;
        unsigned long Size;
@@ -272,6 +284,7 @@ typedef struct drm_i915_private {
                struct drm_mm gtt_space;
 
                struct io_mapping *gtt_mapping;
+               int gtt_mtrr;
 
                /**
                 * List of objects currently involved in rendering from the
@@ -358,6 +371,9 @@ typedef struct drm_i915_private {
                uint32_t bit_6_swizzle_x;
                /** Bit 6 swizzling required for Y tiling */
                uint32_t bit_6_swizzle_y;
+
+               /* storage for physical objects */
+               struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
        } mm;
 } drm_i915_private_t;
 
@@ -436,6 +452,9 @@ struct drm_i915_gem_object {
        /** User space pin count and filp owning the pin */
        uint32_t user_pin_count;
        struct drm_file *pin_filp;
+
+       /** for phy allocated objects */
+       struct drm_i915_gem_phys_object *phys_obj;
 };
 
 /**
@@ -598,6 +617,11 @@ int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
                                      int write);
+int i915_gem_attach_phys_object(struct drm_device *dev,
+                               struct drm_gem_object *obj, int id);
+void i915_gem_detach_phys_object(struct drm_device *dev,
+                                struct drm_gem_object *obj);
+void i915_gem_free_all_phys_object(struct drm_device *dev);
 
 /* i915_gem_tiling.c */
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
@@ -664,6 +688,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
                                 writel(upper_32_bits(val), dev_priv->regs + \
                                        (reg) + 4))
 #endif
+#define POSTING_READ(reg)      (void)I915_READ(reg)
 
 #define I915_VERBOSE 0
 
@@ -760,6 +785,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
                        IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 
 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
+#define SUPPORTS_INTEGRATED_HDMI(dev)  (IS_G4X(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)