drm/i915/debugfs: Print sink PSR status

[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a6c70ff4ae5aab1cd67695dd15544c8c6002bdb4..cb1a804bf72e5836e8bbfbfcc2db8d644bc7ce2b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
        return "unknown";
 }
 
+static const char *psr_sink_status(u8 val)
+{
+       static const char * const sink_status[] = {
+               "inactive",
+               "transition to active, capture and display",
+               "active, display from RFB",
+               "active, capture and display on sink device timings",
+               "transition to inactive, capture and display, timing re-sync",
+               "reserved",
+               "reserved",
+               "sink internal error"
+       };
+
+       val &= DP_PSR_SINK_STATE_MASK;
+       if (val < ARRAY_SIZE(sink_status))
+               return sink_status[val];
+
+       return "unknown";
+}
+
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2684,8 +2704,24 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
                seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
                           psr2, psr2_live_status(psr2));
        }
+
+       if (dev_priv->psr.enabled) {
+               struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
+               u8 val;
+
+               if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1)
+                       seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
+                                  psr_sink_status(val));
+       }
        mutex_unlock(&dev_priv->psr.lock);
 
+       if (READ_ONCE(dev_priv->psr.debug)) {
+               seq_printf(m, "Last attempted entry at: %lld\n",
+                          dev_priv->psr.last_entry_attempt);
+               seq_printf(m, "Last exit at: %lld\n",
+                          dev_priv->psr.last_exit);
+       }
+
        intel_runtime_pm_put(dev_priv);
        return 0;
 }
@@ -4197,119 +4233,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
                        i915_drop_caches_get, i915_drop_caches_set,
                        "0x%08llx\n");
 
-static int
-i915_max_freq_get(void *data, u64 *val)
-{
-       struct drm_i915_private *dev_priv = data;
-
-       if (INTEL_GEN(dev_priv) < 6)
-               return -ENODEV;
-
-       *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
-       return 0;
-}
-
-static int
-i915_max_freq_set(void *data, u64 val)
-{
-       struct drm_i915_private *dev_priv = data;
-       struct intel_rps *rps = &dev_priv->gt_pm.rps;
-       u32 hw_max, hw_min;
-       int ret;
-
-       if (INTEL_GEN(dev_priv) < 6)
-               return -ENODEV;
-
-       DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
-
-       ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
-       if (ret)
-               return ret;
-
-       /*
-        * Turbo will still be enabled, but won't go above the set value.
-        */
-       val = intel_freq_opcode(dev_priv, val);
-
-       hw_max = rps->max_freq;
-       hw_min = rps->min_freq;
-
-       if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
-               mutex_unlock(&dev_priv->pcu_lock);
-               return -EINVAL;
-       }
-
-       rps->max_freq_softlimit = val;
-
-       if (intel_set_rps(dev_priv, val))
-               DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
-
-       mutex_unlock(&dev_priv->pcu_lock);
-
-       return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
-                       i915_max_freq_get, i915_max_freq_set,
-                       "%llu\n");
-
-static int
-i915_min_freq_get(void *data, u64 *val)
-{
-       struct drm_i915_private *dev_priv = data;
-
-       if (INTEL_GEN(dev_priv) < 6)
-               return -ENODEV;
-
-       *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
-       return 0;
-}
-
-static int
-i915_min_freq_set(void *data, u64 val)
-{
-       struct drm_i915_private *dev_priv = data;
-       struct intel_rps *rps = &dev_priv->gt_pm.rps;
-       u32 hw_max, hw_min;
-       int ret;
-
-       if (INTEL_GEN(dev_priv) < 6)
-               return -ENODEV;
-
-       DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
-
-       ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
-       if (ret)
-               return ret;
-
-       /*
-        * Turbo will still be enabled, but won't go below the set value.
-        */
-       val = intel_freq_opcode(dev_priv, val);
-
-       hw_max = rps->max_freq;
-       hw_min = rps->min_freq;
-
-       if (val < hw_min ||
-           val > hw_max || val > rps->max_freq_softlimit) {
-               mutex_unlock(&dev_priv->pcu_lock);
-               return -EINVAL;
-       }
-
-       rps->min_freq_softlimit = val;
-
-       if (intel_set_rps(dev_priv, val))
-               DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
-
-       mutex_unlock(&dev_priv->pcu_lock);
-
-       return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
-                       i915_min_freq_get, i915_min_freq_set,
-                       "%llu\n");
-
 static int
 i915_cache_sharing_get(void *data, u64 *val)
 {
@@ -4871,8 +4794,6 @@ static const struct i915_debugfs_files {
        const struct file_operations *fops;
 } i915_debugfs_files[] = {
        {"i915_wedged", &i915_wedged_fops},
-       {"i915_max_freq", &i915_max_freq_fops},
-       {"i915_min_freq", &i915_min_freq_fops},
        {"i915_cache_sharing", &i915_cache_sharing_fops},
        {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
        {"i915_ring_test_irq", &i915_ring_test_irq_fops},