Merge tag 'gvt-next-2020-04-22' of https://github.com/intel/gvt-linux into drm-intel...

[linux-block.git] / drivers / gpu / drm / i915 / gvt / scheduler.c

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 92a055c9d8d891dc18883fc65da2f0b1dd6f86d2..35ad540622ac82697c1dbd704faf356b0564fbe8 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -331,17 +331,17 @@ static void
 shadow_context_descriptor_update(struct intel_context *ce,
                                 struct intel_vgpu_workload *workload)
 {
-       u64 desc = ce->lrc_desc;
+       u64 desc = ce->lrc.desc;
 
        /*
         * Update bits 0-11 of the context descriptor which includes flags
         * like GEN8_CTX_* cached in desc_template
         */
-       desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
-       desc |= workload->ctx_desc.addressing_mode <<
+       desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);
+       desc |= (u64)workload->ctx_desc.addressing_mode <<
                GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
-       ce->lrc_desc = desc;
+       ce->lrc.desc = desc;
 }
 
 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
@@ -636,10 +636,9 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
                        if (bb->va && !IS_ERR(bb->va))
                                i915_gem_object_unpin_map(bb->obj);
 
-                       if (bb->vma && !IS_ERR(bb->vma)) {
+                       if (bb->vma && !IS_ERR(bb->vma))
                                i915_vma_unpin(bb->vma);
-                               i915_vma_close(bb->vma);
-                       }
+
                        i915_gem_object_put(bb->obj);
                }
                list_del(&bb->list);
@@ -1287,7 +1286,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
                ce->vm = i915_vm_get(&ppgtt->vm);
                intel_context_set_single_submission(ce);
 
-               if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
+               /* Max ring buffer size */
+               if (!intel_uc_wants_guc_submission(&engine->gt->uc)) {
                        const unsigned int ring_size = 512 * SZ_4K;
 
                        ce->ring = __intel_context_ring_size(ring_size);