Merge drm/drm-next into drm-intel-gt-next

[linux-block.git] / drivers / gpu / drm / i915 / gt / intel_gt_regs.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c3cd926917957f629be21c77956e433dd49da586..f8eb807b56f9de765257822b01d8ff5f3225c145 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -67,6 +67,7 @@
 #define GMD_ID_MEDIA                           _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
 
 #define MCFG_MCR_SELECTOR                      _MMIO(0xfd0)
+#define MTL_STEER_SEMAPHORE                    _MMIO(0xfd0)
 #define MTL_MCR_SELECTOR                       _MMIO(0xfd4)
 #define SF_MCR_SELECTOR                                _MMIO(0xfd8)
 #define GEN8_MCR_SELECTOR                      _MMIO(0xfdc)
@@ -429,9 +430,10 @@
 #define   RC_OP_FLUSH_ENABLE                   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE            (1 << 2)
 #define CACHE_MODE_1                           _MMIO(0x7004) /* IVB+ */
-#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE    (1 << 6)
-#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    (1 << 6)
-#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE      REG_BIT(11)
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE    REG_BIT(6)
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    REG_BIT(6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
 
 #define GEN7_GT_MODE                           _MMIO(0x7008)
 #define   GEN9_IZ_HASHING_MASK(slice)          (0x3 << ((slice) * 2))
@@ -457,6 +459,9 @@
 #define GEN8_L3CNTLREG                         _MMIO(0x7034)
 #define   GEN8_ERRDETBCTRL                     (1 << 9)
 
+#define PSS_MODE2                              _MMIO(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL       REG_BIT(5)
+
 #define GEN7_SC_INSTDONE                       _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA                        _MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2               _MMIO(0x7108)
@@ -917,6 +922,10 @@
 #define  MSG_IDLE_FW_MASK      REG_GENMASK(13, 9)
 #define  MSG_IDLE_FW_SHIFT     9
 
+#define        RC_PSMI_CTRL_GSCCS      _MMIO(0x11a050)
+#define          IDLE_MSG_DISABLE      REG_BIT(0)
+#define        PWRCTX_MAXCNT_GSCCS     _MMIO(0x11a054)
+
 #define FORCEWAKE_MEDIA_GEN9                   _MMIO(0xa270)
 #define FORCEWAKE_RENDER_GEN9                  _MMIO(0xa278)
 
@@ -949,10 +958,11 @@
 #define   GEN7_DISABLE_SAMPLER_PREFETCH                (1 << 30)
 
 #define GEN8_GARBCNTL                          _MMIO(0xb004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE         (1 << 7)
-#define   GEN11_ARBITRATION_PRIO_ORDER_MASK    (0x3f << 22)
-#define   GEN11_HASH_CTRL_EXCL_MASK            (0x7f << 0)
-#define   GEN11_HASH_CTRL_EXCL_BIT0            (1 << 0)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK    REG_GENMASK(27, 22)
+#define   GEN12_BUS_HASH_CTL_BIT_EXC           REG_BIT(7)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE         REG_BIT(7)
+#define   GEN11_HASH_CTRL_EXCL_MASK            REG_GENMASK(6, 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0            REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)
 
 #define GEN9_SCRATCH_LNCF1                     _MMIO(0xb008)
 #define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE      REG_BIT(0)
@@ -965,6 +975,7 @@
 #define   GEN7_L3AGDIS                         (1 << 19)
 
 #define XEHPC_LNCFMISCCFGREG0                  _MMIO(0xb01c)
+#define   XEHPC_HOSTCACHEEN                    REG_BIT(1)
 #define   XEHPC_OVRLSCCC                       REG_BIT(0)
 
 #define GEN7_L3CNTLREG2                                _MMIO(0xb020)