drm/i915: move dpll under display.dpll

[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_display.c

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 903226e2a6260d98de9a6d44022ef9d73f802f28..9dee856416321f44d1cbc57fb187ca392f237716 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,8 +126,6 @@
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
-static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -167,16 +165,16 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
  */
 void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-       if (dev_priv->wm_disp->update_wm)
-               dev_priv->wm_disp->update_wm(dev_priv);
+       if (dev_priv->display.funcs.wm->update_wm)
+               dev_priv->display.funcs.wm->update_wm(dev_priv);
 }
 
 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
                                 struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (dev_priv->wm_disp->compute_pipe_wm)
-               return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
+       if (dev_priv->display.funcs.wm->compute_pipe_wm)
+               return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
        return 0;
 }
 
@@ -184,20 +182,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
                                         struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (!dev_priv->wm_disp->compute_intermediate_wm)
+       if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
                return 0;
        if (drm_WARN_ON(&dev_priv->drm,
-                       !dev_priv->wm_disp->compute_pipe_wm))
+                       !dev_priv->display.funcs.wm->compute_pipe_wm))
                return 0;
-       return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
+       return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
 }
 
 static bool intel_initial_watermarks(struct intel_atomic_state *state,
                                     struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (dev_priv->wm_disp->initial_watermarks) {
-               dev_priv->wm_disp->initial_watermarks(state, crtc);
+       if (dev_priv->display.funcs.wm->initial_watermarks) {
+               dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
                return true;
        }
        return false;
@@ -207,23 +205,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
                                           struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (dev_priv->wm_disp->atomic_update_watermarks)
-               dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
+       if (dev_priv->display.funcs.wm->atomic_update_watermarks)
+               dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
 }
 
 static void intel_optimize_watermarks(struct intel_atomic_state *state,
                                      struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (dev_priv->wm_disp->optimize_watermarks)
-               dev_priv->wm_disp->optimize_watermarks(state, crtc);
+       if (dev_priv->display.funcs.wm->optimize_watermarks)
+               dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
 }
 
 static int intel_compute_global_watermarks(struct intel_atomic_state *state)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-       if (dev_priv->wm_disp->compute_global_watermarks)
-               return dev_priv->wm_disp->compute_global_watermarks(state);
+       if (dev_priv->display.funcs.wm->compute_global_watermarks)
+               return dev_priv->display.funcs.wm->compute_global_watermarks(state);
        return 0;
 }
 
@@ -1490,7 +1488,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
         * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
         * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
         */
-       if (i915->dpll.mgr) {
+       if (i915->display.dpll.mgr) {
                for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
                        if (intel_crtc_needs_modeset(new_crtc_state))
                                continue;
@@ -2084,22 +2082,20 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
        if (phy == PHY_NONE)
                return false;
-       else if (IS_DG2(dev_priv))
-               /*
-                * DG2 outputs labelled as "combo PHY" in the bspec use
-                * SNPS PHYs with completely different programming,
-                * hence we always return false here.
-                */
-               return false;
        else if (IS_ALDERLAKE_S(dev_priv))
                return phy <= PHY_E;
        else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
                return phy <= PHY_D;
        else if (IS_JSL_EHL(dev_priv))
                return phy <= PHY_C;
-       else if (DISPLAY_VER(dev_priv) >= 11)
+       else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
                return phy <= PHY_B;
        else
+               /*
+                * DG2 outputs labelled as "combo PHY" in the bspec use
+                * SNPS PHYs with completely different programming,
+                * hence we always return false here.
+                */
                return false;
 }
 
@@ -2405,7 +2401,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
        if (DISPLAY_VER(dev_priv) != 2)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-       if (!dev_priv->wm_disp->initial_watermarks)
+       if (!dev_priv->display.funcs.wm->initial_watermarks)
                intel_update_watermarks(dev_priv);
 
        /* clock the pipe down to 640x480@60 to potentially save power */
@@ -3015,14 +3011,18 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
        intel_bigjoiner_adjust_pipe_src(pipe_config);
 }
 
-static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
+void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        u32 pipeconf = 0;
 
-       /* we keep both pipes enabled on 830 */
-       if (IS_I830(dev_priv))
+       /*
+        * - We keep both pipes enabled on 830
+        * - During modeset the pipe is still disabled and must remain so
+        * - During fastset the pipe is already enabled and must remain so
+        */
+       if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
                pipeconf |= PIPECONF_ENABLE;
 
        if (crtc_state->double_wide)
@@ -3335,14 +3335,19 @@ out:
        return ret;
 }
 
-static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
+void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
-       u32 val;
+       u32 val = 0;
 
-       val = 0;
+       /*
+        * - During modeset the pipe is still disabled and must remain so
+        * - During fastset the pipe is already enabled and must remain so
+        */
+       if (!intel_crtc_needs_modeset(crtc_state))
+               val |= PIPECONF_ENABLE;
 
        switch (crtc_state->pipe_bpp) {
        default:
@@ -3401,6 +3406,13 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        u32 val = 0;
 
+       /*
+        * - During modeset the pipe is still disabled and must remain so
+        * - During fastset the pipe is already enabled and must remain so
+        */
+       if (!intel_crtc_needs_modeset(crtc_state))
+               val |= PIPECONF_ENABLE;
+
        if (IS_HASWELL(dev_priv) && crtc_state->dither)
                val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
 
@@ -4133,7 +4145,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-       if (!i915->display->get_pipe_config(crtc, crtc_state))
+       if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
                return false;
 
        crtc_state->hw.active = true;
@@ -5828,7 +5840,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
        PIPE_CONF_CHECK_BOOL(double_wide);
 
-       if (dev_priv->dpll.mgr) {
+       if (dev_priv->display.dpll.mgr) {
                PIPE_CONF_CHECK_P(shared_dpll);
 
                PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
@@ -7108,7 +7120,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 
        intel_crtc_update_active_timings(new_crtc_state);
 
-       dev_priv->display->crtc_enable(state, crtc);
+       dev_priv->display.funcs.display->crtc_enable(state, crtc);
 
        if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
                return;
@@ -7187,7 +7199,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
         */
        intel_crtc_disable_pipe_crc(crtc);
 
-       dev_priv->display->crtc_disable(state, crtc);
+       dev_priv->display.funcs.display->crtc_disable(state, crtc);
        crtc->active = false;
        intel_fbc_disable(crtc);
        intel_disable_shared_dpll(old_crtc_state);
@@ -7575,7 +7587,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
        }
 
        /* Now enable the clocks, plane, pipe, and connectors that we set up. */
-       dev_priv->display->commit_modeset_enables(state);
+       dev_priv->display.funcs.display->commit_modeset_enables(state);
 
        intel_encoders_update_complete(state);
 
@@ -8306,7 +8318,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
        .atomic_state_free = intel_atomic_state_free,
 };
 
-static const struct drm_i915_display_funcs skl_display_funcs = {
+static const struct intel_display_funcs skl_display_funcs = {
        .get_pipe_config = hsw_get_pipe_config,
        .crtc_enable = hsw_crtc_enable,
        .crtc_disable = hsw_crtc_disable,
@@ -8314,7 +8326,7 @@ static const struct drm_i915_display_funcs skl_display_funcs = {
        .get_initial_plane_config = skl_get_initial_plane_config,
 };
 
-static const struct drm_i915_display_funcs ddi_display_funcs = {
+static const struct intel_display_funcs ddi_display_funcs = {
        .get_pipe_config = hsw_get_pipe_config,
        .crtc_enable = hsw_crtc_enable,
        .crtc_disable = hsw_crtc_disable,
@@ -8322,7 +8334,7 @@ static const struct drm_i915_display_funcs ddi_display_funcs = {
        .get_initial_plane_config = i9xx_get_initial_plane_config,
 };
 
-static const struct drm_i915_display_funcs pch_split_display_funcs = {
+static const struct intel_display_funcs pch_split_display_funcs = {
        .get_pipe_config = ilk_get_pipe_config,
        .crtc_enable = ilk_crtc_enable,
        .crtc_disable = ilk_crtc_disable,
@@ -8330,7 +8342,7 @@ static const struct drm_i915_display_funcs pch_split_display_funcs = {
        .get_initial_plane_config = i9xx_get_initial_plane_config,
 };
 
-static const struct drm_i915_display_funcs vlv_display_funcs = {
+static const struct intel_display_funcs vlv_display_funcs = {
        .get_pipe_config = i9xx_get_pipe_config,
        .crtc_enable = valleyview_crtc_enable,
        .crtc_disable = i9xx_crtc_disable,
@@ -8338,7 +8350,7 @@ static const struct drm_i915_display_funcs vlv_display_funcs = {
        .get_initial_plane_config = i9xx_get_initial_plane_config,
 };
 
-static const struct drm_i915_display_funcs i9xx_display_funcs = {
+static const struct intel_display_funcs i9xx_display_funcs = {
        .get_pipe_config = i9xx_get_pipe_config,
        .crtc_enable = i9xx_crtc_enable,
        .crtc_disable = i9xx_crtc_disable,
@@ -8361,16 +8373,16 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
        intel_dpll_init_clock_hook(dev_priv);
 
        if (DISPLAY_VER(dev_priv) >= 9) {
-               dev_priv->display = &skl_display_funcs;
+               dev_priv->display.funcs.display = &skl_display_funcs;
        } else if (HAS_DDI(dev_priv)) {
-               dev_priv->display = &ddi_display_funcs;
+               dev_priv->display.funcs.display = &ddi_display_funcs;
        } else if (HAS_PCH_SPLIT(dev_priv)) {
-               dev_priv->display = &pch_split_display_funcs;
+               dev_priv->display.funcs.display = &pch_split_display_funcs;
        } else if (IS_CHERRYVIEW(dev_priv) ||
                   IS_VALLEYVIEW(dev_priv)) {
-               dev_priv->display = &vlv_display_funcs;
+               dev_priv->display.funcs.display = &vlv_display_funcs;
        } else {
-               dev_priv->display = &i9xx_display_funcs;
+               dev_priv->display.funcs.display = &i9xx_display_funcs;
        }
 
        intel_fdi_init_hook(dev_priv);
@@ -8443,7 +8455,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
        int i;
 
        /* Only supported on platforms that use atomic watermark design */
-       if (!dev_priv->wm_disp->optimize_watermarks)
+       if (!dev_priv->display.funcs.wm->optimize_watermarks)
                return;
 
        state = drm_atomic_state_alloc(&dev_priv->drm);