Merge tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...

[linux-2.6-block.git] / drivers / gpu / drm / gma500 / psb_drv.h

diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 821497dbd3fcbee99b2feb4e7a2890b2b40f213f..e8300f50902343957e2967a9cd581244a5bf01ad 100644 (file)
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -36,7 +36,6 @@
 #include "mmu.h"
 
 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
-#define DRIVER_LICENSE "GPL"
 
 #define DRIVER_NAME "gma500"
 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
@@ -781,38 +780,40 @@ extern const struct psb_ops cdv_chip_ops;
 extern int drm_idle_check_interval;
 
 /* Utilities */
-static inline u32 MRST_MSG_READ32(uint port, uint offset)
+static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
 {
        int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
        uint32_t ret_val = 0;
-       struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+       struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
        pci_write_config_dword(pci_root, 0xD0, mcr);
        pci_read_config_dword(pci_root, 0xD4, &ret_val);
        pci_dev_put(pci_root);
        return ret_val;
 }
-static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
+static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
+                                   u32 value)
 {
        int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
-       struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+       struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
        pci_write_config_dword(pci_root, 0xD4, value);
        pci_write_config_dword(pci_root, 0xD0, mcr);
        pci_dev_put(pci_root);
 }
-static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
+static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
 {
        int mcr = (0x10<<24) | (port << 16) | (offset << 8);
        uint32_t ret_val = 0;
-       struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+       struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
        pci_write_config_dword(pci_root, 0xD0, mcr);
        pci_read_config_dword(pci_root, 0xD4, &ret_val);
        pci_dev_put(pci_root);
        return ret_val;
 }
-static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
+static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
+                                    u32 value)
 {
        int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
-       struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+       struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
        pci_write_config_dword(pci_root, 0xD4, value);
        pci_write_config_dword(pci_root, 0xD0, mcr);
        pci_dev_put(pci_root);