Merge tag 'amd-drm-next-5.8-2020-04-30' of git://people.freedesktop.org/~agd5f/linux...

[linux-block.git] / drivers / gpu / drm / amd / powerplay / smu_v11_0.c

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 0045b54b19ed9b35efe16ad5ebfe005beb7c1e52..d5a3487ccfacfd2c4fbadba16c66484af9578bd0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -57,7 +57,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
                                              uint16_t msg)
 {
        struct amdgpu_device *adev = smu->adev;
-       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
        return 0;
 }
 
@@ -65,7 +65,7 @@ static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
 {
        struct amdgpu_device *adev = smu->adev;
 
-       *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+       *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82);
        return 0;
 }
 
@@ -75,7 +75,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
        uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
 
        for (i = 0; i < timeout; i++) {
-               cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+               cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);
                if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
                        return cur_value == 0x1 ? 0 : -EIO;
 
@@ -83,7 +83,10 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
        }
 
        /* timeout means wrong logic */
-       return -ETIME;
+       if (i == timeout)
+               return -ETIME;
+
+       return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
 }
 
 int
@@ -107,9 +110,9 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
                goto out;
        }
 
-       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
-       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 
        smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 
@@ -119,6 +122,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
                       smu_get_message_name(smu, msg), index, param, ret);
                goto out;
        }
+
        if (read_arg) {
                ret = smu_v11_0_read_arg(smu, read_arg);
                if (ret) {
@@ -728,8 +732,9 @@ int smu_v11_0_parse_pptable(struct smu_context *smu)
        struct smu_table_context *table_context = &smu->smu_table;
        struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 
+       /* during TDR we need to free and alloc the pptable */
        if (table_context->driver_pptable)
-               return -EINVAL;
+               kfree(table_context->driver_pptable);
 
        table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 
@@ -769,6 +774,9 @@ int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 {
        int ret;
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
        ret = smu_send_smc_msg_with_param(smu,
                                          SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
        if (ret)
@@ -812,6 +820,9 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)
        int ret = 0;
        struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
        if (tool_table->mc_address) {
                ret = smu_send_smc_msg_with_param(smu,
                                SMU_MSG_SetToolsDramAddrHigh,
@@ -831,6 +842,12 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 {
        int ret = 0;
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
+       if (!smu->pm_enabled)
+               return ret;
+
        ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
        return ret;
 }
@@ -842,6 +859,9 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
        int ret = 0;
        uint32_t feature_mask[2];
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
        mutex_lock(&feature->mutex);
        if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
                goto failed;
@@ -870,6 +890,9 @@ int smu_v11_0_get_enabled_mask(struct smu_context *smu,
        struct smu_feature *feature = &smu->smu_feature;
        int ret = 0;
 
+       if (amdgpu_sriov_vf(smu->adev) && !amdgpu_sriov_is_pp_one_vf(smu->adev))
+               return 0;
+
        if (!feature_mask || num < 2)
                return -EINVAL;
 
@@ -925,6 +948,12 @@ int smu_v11_0_notify_display_change(struct smu_context *smu)
 {
        int ret = 0;
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
+       if (!smu->pm_enabled)
+               return ret;
+
        if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
            smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
                ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
@@ -1084,6 +1113,9 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
        int ret = 0;
        uint32_t max_power_limit;
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
        max_power_limit = smu_v11_0_get_max_power_limit(smu);
 
        if (n > max_power_limit) {
@@ -1815,6 +1847,9 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
        uint32_t pcie_gen = 0, pcie_width = 0;
        int ret;
 
+       if (amdgpu_sriov_vf(smu->adev))
+               return 0;
+
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
                pcie_gen = 3;
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)