drm/amd/display: add CLKMGR changes for DCN32/321

[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / inc / hw / clk_mgr_internal.h

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 1391c20f18524dd7afe493a92c2befb628413ecc..68c2ed434d2c4fb9ce5644c9789359d6bcb21a32 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -112,9 +112,10 @@ enum dentist_divider_range {
        CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
        CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
 
-// TODO:
 #define CLK_REG_LIST_DCN3()      \
-       SR(DENTIST_DISPCLK_CNTL)
+       CLK_COMMON_REG_LIST_DCN_BASE(), \
+       CLK_SRI(CLK0_CLK_PLL_REQ,   CLK02, 0), \
+       CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
 
 #define CLK_SF(reg_name, field_name, post_fix)\
        .field_name = reg_name ## __ ## field_name ## post_fix
@@ -155,6 +156,34 @@ enum dentist_divider_range {
        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
        CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
 
+#define CLK_REG_LIST_DCN32()     \
+       SR(DENTIST_DISPCLK_CNTL), \
+       CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
+       CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
+       CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
+       CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
+       CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
+       CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+       CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+       CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
+       CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
+#define CLK_REG_LIST_DCN321()    \
+       SR(DENTIST_DISPCLK_CNTL), \
+       CLK_SR_DCN321(CLK0_CLK_PLL_REQ,   CLK01, 0), \
+       CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
+       CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
+       CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
+       CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
+       CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
+       CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+       CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
+       CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
 #define CLK_REG_FIELD_LIST(type) \
        type DPREFCLK_SRC_SEL; \
        type DENTIST_DPREFCLK_WDIVIDER; \
@@ -199,6 +228,18 @@ struct clk_mgr_registers {
        uint32_t CLK0_CLK2_DFS_CNTL;
        uint32_t CLK0_CLK_PLL_REQ;
 
+       uint32_t CLK1_CLK_PLL_REQ;
+       uint32_t CLK1_CLK0_DFS_CNTL;
+       uint32_t CLK1_CLK1_DFS_CNTL;
+       uint32_t CLK1_CLK2_DFS_CNTL;
+       uint32_t CLK1_CLK3_DFS_CNTL;
+       uint32_t CLK1_CLK4_DFS_CNTL;
+
+       uint32_t CLK0_CLK0_DFS_CNTL;
+       uint32_t CLK0_CLK1_DFS_CNTL;
+       uint32_t CLK0_CLK3_DFS_CNTL;
+       uint32_t CLK0_CLK4_DFS_CNTL;
+
        uint32_t MP1_SMN_C2PMSG_67;
        uint32_t MP1_SMN_C2PMSG_83;
        uint32_t MP1_SMN_C2PMSG_91;