drm/amd/display: Drop DCN for DP2.x logic
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
index f1593186e964d9f58982f7ab8f45c2938c9e57a0..b83c5544247d8d72688db10aff35bd6cfd1dd4f4 100644 (file)
@@ -49,9 +49,7 @@
 #include "link_enc_cfg.h"
 #include "link_hwss.h"
 #include "dc_link_dp.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
 #include "dccg.h"
-#endif
 #include "clock_source.h"
 #include "clk_mgr.h"
 #include "abm.h"
@@ -1112,17 +1110,12 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
                        clk_mgr->funcs->enable_pme_wa(clk_mgr);
                /* un-mute audio */
                /* TODO: audio should be per stream rather than per link */
-#if defined(CONFIG_DRM_AMD_DC_DCN)
                if (is_dp_128b_132b_signal(pipe_ctx))
                        pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
                                        pipe_ctx->stream_res.hpo_dp_stream_enc, false);
                else
                        pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
                                        pipe_ctx->stream_res.stream_enc, false);
-#else
-               pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-                               pipe_ctx->stream_res.stream_enc, false);
-#endif
                if (pipe_ctx->stream_res.audio)
                        pipe_ctx->stream_res.audio->enabled = true;
        }
@@ -1145,32 +1138,22 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
        if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
                return;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (is_dp_128b_132b_signal(pipe_ctx))
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
                                pipe_ctx->stream_res.hpo_dp_stream_enc, true);
        else
                pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
                                pipe_ctx->stream_res.stream_enc, true);
-#else
-       pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-                       pipe_ctx->stream_res.stream_enc, true);
-#endif
        if (pipe_ctx->stream_res.audio) {
                pipe_ctx->stream_res.audio->enabled = false;
 
                if (dc_is_dp_signal(pipe_ctx->stream->signal))
-#if defined(CONFIG_DRM_AMD_DC_DCN)
                        if (is_dp_128b_132b_signal(pipe_ctx))
                                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(
                                                pipe_ctx->stream_res.hpo_dp_stream_enc);
                        else
                                pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
                                                pipe_ctx->stream_res.stream_enc);
-#else
-                       pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
-                                       pipe_ctx->stream_res.stream_enc);
-#endif
                else
                        pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
                                        pipe_ctx->stream_res.stream_enc);
@@ -1204,14 +1187,10 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
                        pipe_ctx->stream_res.stream_enc);
        }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (is_dp_128b_132b_signal(pipe_ctx)) {
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
                                        pipe_ctx->stream_res.hpo_dp_stream_enc);
        } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
-#else
-       if (dc_is_dp_signal(pipe_ctx->stream->signal))
-#endif
                pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
                        pipe_ctx->stream_res.stream_enc);
 
@@ -1224,7 +1203,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
                link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
        ASSERT(link_enc);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (is_dp_128b_132b_signal(pipe_ctx)) {
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable(
                                pipe_ctx->stream_res.hpo_dp_stream_enc);
@@ -1237,13 +1215,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
                                pipe_ctx->stream_res.stream_enc->id,
                                false);
        }
-#else
-       if (link_enc)
-               link_enc->funcs->connect_dig_be_to_fe(
-                       link->link_enc,
-                       pipe_ctx->stream_res.stream_enc->id,
-                       false);
-#endif
+
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
 
@@ -1285,15 +1257,11 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
                link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
        }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (is_dp_128b_132b_signal(pipe_ctx)) {
                /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
                                pipe_ctx->stream_res.hpo_dp_stream_enc);
        } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
-#else
-       if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
-#endif
                pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
 
                if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
@@ -1535,7 +1503,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
                build_audio_output(context, pipe_ctx, &audio_output);
 
                if (dc_is_dp_signal(pipe_ctx->stream->signal))
-#if defined(CONFIG_DRM_AMD_DC_DCN)
                        if (is_dp_128b_132b_signal(pipe_ctx))
                                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
                                                pipe_ctx->stream_res.hpo_dp_stream_enc,
@@ -1546,12 +1513,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
                                                pipe_ctx->stream_res.stream_enc,
                                                pipe_ctx->stream_res.audio->inst,
                                                &pipe_ctx->stream->audio_info);
-#else
-                       pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
-                                       pipe_ctx->stream_res.stream_enc,
-                                       pipe_ctx->stream_res.audio->inst,
-                                       &pipe_ctx->stream->audio_info);
-#endif
                else
                        pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
                                        pipe_ctx->stream_res.stream_enc,
@@ -1570,14 +1531,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
                check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        /* DCN3.1 FPGA Workaround
         * Need to enable HPO DP Stream Encoder before setting OTG master enable.
         * To do so, move calling function enable_stream_timing to only be done AFTER calling
         * function core_link_enable_stream
         */
        if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
-#endif
                /*  */
                /* Do not touch stream timing on seamless boot optimization. */
                if (!pipe_ctx->stream->apply_seamless_boot_optimization)
@@ -1608,7 +1567,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
                        pipe_ctx->stream_res.stream_enc,
                        pipe_ctx->stream_res.tg->inst);
 
-       if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
+       if (dc_is_embedded_signal(pipe_ctx->stream->signal) &&
                pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
                pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
                        pipe_ctx->stream_res.stream_enc);
@@ -1643,7 +1602,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        if (!stream->dpms_off)
                core_link_enable_stream(context, pipe_ctx);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        /* DCN3.1 FPGA Workaround
         * Need to enable HPO DP Stream Encoder before setting OTG master enable.
         * To do so, move calling function enable_stream_timing to only be done AFTER calling
@@ -1653,7 +1611,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
                if (!pipe_ctx->stream->apply_seamless_boot_optimization)
                        hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
        }
-#endif
 
        pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
 
@@ -2233,8 +2190,6 @@ static void dce110_setup_audio_dto(
 
                        build_audio_output(context, pipe_ctx, &audio_output);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-                       /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
                        if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
                                /* disable audio DTBCLK DTO */
                                dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
@@ -2251,13 +2206,6 @@ static void dce110_setup_audio_dto(
                                        pipe_ctx->stream->signal,
                                        &audio_output.crtc_info,
                                        &audio_output.pll_info);
-#else
-                       pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
-                               pipe_ctx->stream_res.audio,
-                               pipe_ctx->stream->signal,
-                               &audio_output.crtc_info,
-                               &audio_output.pll_info);
-#endif
                        break;
                }
        }