drm/amd/display: Add DCN3 CLK_MGR

[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_stream.c

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 6ddbb00ed37a5aa5f0b53a525995bb327bc882b7..3b897372ed2782260b163919942fe3e822da3612 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -231,34 +231,6 @@ struct dc_stream_status *dc_stream_get_status(
        return dc_stream_get_status_from_state(dc->current_state, stream);
 }
 
-static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
-{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-       unsigned int vupdate_line;
-       unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
-       struct dc_stream_state *stream = pipe_ctx->stream;
-       unsigned int us_per_line;
-
-       if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
-                       ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
-
-               vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
-               if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
-                       return;
-
-               if (vpos >= vupdate_line)
-                       return;
-
-               us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz;
-               lines_to_vupdate = vupdate_line - vpos;
-               us_to_vupdate = lines_to_vupdate * us_per_line;
-
-               /* 70 us is a conservative estimate of cursor update time*/
-               if (us_to_vupdate < 70)
-                       udelay(us_to_vupdate);
-       }
-#endif
-}
 
 /**
  * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
@@ -271,6 +243,9 @@ bool dc_stream_set_cursor_attributes(
        struct dc  *dc;
        struct resource_context *res_ctx;
        struct pipe_ctx *pipe_to_program = NULL;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       bool reset_idle_optimizations = false;
+#endif
 
        if (NULL == stream) {
                dm_error("DC: dc_stream is NULL!\n");
@@ -290,6 +265,15 @@ bool dc_stream_set_cursor_attributes(
        res_ctx = &dc->current_state->res_ctx;
        stream->cursor_attributes = *attributes;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       /* disable idle optimizations while updating cursor */
+       if (dc->idle_optimizations_allowed) {
+               dc->hwss.apply_idle_power_optimizations(dc, false);
+               reset_idle_optimizations = true;
+       }
+
+#endif
+
        for (i = 0; i < MAX_PIPES; i++) {
                struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 
@@ -298,9 +282,7 @@ bool dc_stream_set_cursor_attributes(
 
                if (!pipe_to_program) {
                        pipe_to_program = pipe_ctx;
-
-                       delay_cursor_until_vupdate(pipe_ctx, dc);
-                       dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+                       dc->hwss.cursor_lock(dc, pipe_to_program, true);
                }
 
                dc->hwss.set_cursor_attribute(pipe_ctx);
@@ -309,8 +291,14 @@ bool dc_stream_set_cursor_attributes(
        }
 
        if (pipe_to_program)
-               dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+               dc->hwss.cursor_lock(dc, pipe_to_program, false);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       /* re-enable idle optimizations if necessary */
+       if (reset_idle_optimizations)
+               dc->hwss.apply_idle_power_optimizations(dc, true);
 
+#endif
        return true;
 }
 
@@ -322,6 +310,9 @@ bool dc_stream_set_cursor_position(
        struct dc  *dc;
        struct resource_context *res_ctx;
        struct pipe_ctx *pipe_to_program = NULL;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       bool reset_idle_optimizations = false;
+#endif
 
        if (NULL == stream) {
                dm_error("DC: dc_stream is NULL!\n");
@@ -335,6 +326,16 @@ bool dc_stream_set_cursor_position(
 
        dc = stream->ctx->dc;
        res_ctx = &dc->current_state->res_ctx;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+
+       /* disable idle optimizations if enabling cursor */
+       if (dc->idle_optimizations_allowed &&
+                       !stream->cursor_position.enable && position->enable) {
+               dc->hwss.apply_idle_power_optimizations(dc, false);
+               reset_idle_optimizations = true;
+       }
+
+#endif
        stream->cursor_position = *position;
 
        for (i = 0; i < MAX_PIPES; i++) {
@@ -349,17 +350,21 @@ bool dc_stream_set_cursor_position(
 
                if (!pipe_to_program) {
                        pipe_to_program = pipe_ctx;
-
-                       delay_cursor_until_vupdate(pipe_ctx, dc);
-                       dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+                       dc->hwss.cursor_lock(dc, pipe_to_program, true);
                }
 
                dc->hwss.set_cursor_position(pipe_ctx);
        }
 
        if (pipe_to_program)
-               dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+               dc->hwss.cursor_lock(dc, pipe_to_program, false);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       /* re-enable idle optimizations if necessary */
+       if (reset_idle_optimizations)
+               dc->hwss.apply_idle_power_optimizations(dc, true);
 
+#endif
        return true;
 }