drm/amd/display: Add DCN3 DIO

[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link.c

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c08de6823db4b83590603f8e0cb6796c02a7d2c5..cb5491fb326c110dcbe613b40c0dff434838b16f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -521,11 +521,11 @@ static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *lin
 }
 
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
-bool dc_link_is_hdcp14(struct dc_link *link)
+bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 {
        bool ret = false;
 
-       switch (link->connector_signal) {
+       switch (signal) {
        case SIGNAL_TYPE_DISPLAY_PORT:
        case SIGNAL_TYPE_DISPLAY_PORT_MST:
                ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
@@ -545,11 +545,11 @@ bool dc_link_is_hdcp14(struct dc_link *link)
        return ret;
 }
 
-bool dc_link_is_hdcp22(struct dc_link *link)
+bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 {
        bool ret = false;
 
-       switch (link->connector_signal) {
+       switch (signal) {
        case SIGNAL_TYPE_DISPLAY_PORT:
        case SIGNAL_TYPE_DISPLAY_PORT_MST:
                ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
@@ -691,10 +691,9 @@ static bool detect_dp(struct dc_link *link,
        if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
                sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 
-               dpcd_set_source_specific_data(link);
-
                if (!detect_dp_sink_caps(link))
                        return false;
+               dpcd_set_source_specific_data(link);
 
                if (is_mst_supported(link)) {
                        sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
@@ -3134,6 +3133,11 @@ void core_link_enable_stream(
 
        pipe_ctx->stream->link->link_state_valid = true;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+               if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
+                                       pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
+#endif
+
        if (dc_is_dvi_signal(pipe_ctx->stream->signal))
                pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
                        pipe_ctx->stream_res.stream_enc,
@@ -3216,6 +3220,15 @@ void core_link_enable_stream(
                                        CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
                                        COLOR_DEPTH_UNDEFINED);
 
+               /* This second call is needed to reconfigure the DIG
+                * as a workaround for the incorrect value being applied
+                * from transmitter control.
+                */
+               if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+                       stream->link->link_enc->funcs->setup(
+                               stream->link->link_enc,
+                               pipe_ctx->stream->signal);
+
                dc->hwss.enable_stream(pipe_ctx);
 
                /* Set DPS PPS SDP (AKA "info frames") */
@@ -3245,6 +3258,10 @@ void core_link_enable_stream(
                        dp_set_dsc_enable(pipe_ctx, true);
 
        }
+
+       if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+               core_link_set_avmute(pipe_ctx, false);
+       }
 }
 
 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
@@ -3257,6 +3274,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
                        dc_is_virtual_signal(pipe_ctx->stream->signal))
                return;
 
+       if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+               core_link_set_avmute(pipe_ctx, true);
+       }
+
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
        update_psp_stream_config(pipe_ctx, true);
 #endif