Merge tag 'amd-drm-next-6.9-2024-03-01' of https://gitlab.freedesktop.org/agd5f/linux...

[linux-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bcdd4f28b64c60e88d104634962b00d92dec3917..6701f1fde79cf5062ba10b389c7f38519eb928fe 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5235,6 +5235,10 @@ static inline void fill_dc_dirty_rect(struct drm_plane *plane,
  * @new_plane_state: New state of @plane
  * @crtc_state: New state of CRTC connected to the @plane
  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
+ * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled.
+ *             If PSR SU is enabled and damage clips are available, only the regions of the screen
+ *             that have changed will be updated. If PSR SU is not enabled,
+ *             or if damage clips are not available, the entire screen will be updated.
  * @dirty_regions_changed: dirty regions changed
  *
  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
@@ -6229,7 +6233,8 @@ create_stream_for_sink(struct drm_connector *connector,
                 */
                DRM_DEBUG_DRIVER("No preferred mode found\n");
        } else if (aconnector) {
-               recalculate_timing = is_freesync_video_mode(&mode, aconnector);
+               recalculate_timing = amdgpu_freesync_vid_mode &&
+                                is_freesync_video_mode(&mode, aconnector);
                if (recalculate_timing) {
                        freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
                        drm_mode_copy(&saved_mode, &mode);
@@ -6389,9 +6394,6 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
        } else if (property == adev->mode_info.underscan_property) {
                dm_new_state->underscan_enable = val;
                ret = 0;
-       } else if (property == adev->mode_info.abm_level_property) {
-               dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
-               ret = 0;
        }
 
        return ret;
@@ -6434,10 +6436,6 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
        } else if (property == adev->mode_info.underscan_property) {
                *val = dm_state->underscan_enable;
                ret = 0;
-       } else if (property == adev->mode_info.abm_level_property) {
-               *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
-                       dm_state->abm_level : 0;
-               ret = 0;
        }
 
        return ret;
@@ -6656,7 +6654,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
        struct edid *edid;
        struct i2c_adapter *ddc;
 
-       if (dc_link->aux_mode)
+       if (dc_link && dc_link->aux_mode)
                ddc = &aconnector->dm_dp_aux.aux.ddc;
        else
                ddc = &aconnector->i2c->base;
@@ -7547,7 +7545,7 @@ static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connect
        struct amdgpu_dm_connector *amdgpu_dm_connector =
                to_amdgpu_dm_connector(connector);
 
-       if (!edid)
+       if (!(amdgpu_freesync_vid_mode && edid))
                return;
 
        if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
@@ -7664,13 +7662,6 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
        aconnector->base.state->max_bpc = 16;
        aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
 
-       if (connector_type == DRM_MODE_CONNECTOR_eDP &&
-           (dc_is_dmcu_initialized(adev->dm.dc) ||
-            adev->dm.dc->ctx->dmub_srv) && amdgpu_dm_abm_level < 0) {
-               drm_object_attach_property(&aconnector->base.base,
-                               adev->mode_info.abm_level_property, 0);
-       }
-
        if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
                /* Content Type is currently only implemented for HDMI. */
                drm_connector_attach_content_type_property(&aconnector->base);
@@ -9847,7 +9838,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
                 * TODO: Refactor this function to allow this check to work
                 * in all conditions.
                 */
-               if (dm_new_crtc_state->stream &&
+               if (amdgpu_freesync_vid_mode &&
+                   dm_new_crtc_state->stream &&
                    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
                        goto skip_modeset;
 
@@ -9887,7 +9879,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
                }
 
                /* Now check if we should set freesync video mode */
-               if (dm_new_crtc_state->stream &&
+               if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
                    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
                    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
                    is_timing_unchanged_for_freesync(new_crtc_state,
@@ -9900,7 +9892,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
                        set_freesync_fixed_config(dm_new_crtc_state);
 
                        goto skip_modeset;
-               } else if (aconnector &&
+               } else if (amdgpu_freesync_vid_mode && aconnector &&
                           is_freesync_video_mode(&new_crtc_state->mode,
                                                  aconnector)) {
                        struct drm_display_mode *high_mode;