drm/amdgpu: rework IP block registration (v2)
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / uvd_v6_0.c
index aeb1b6e2c518d1e88037dc1ded2961637517ea86..2e2baa614b2849a493490368c5346eb3a932bb2d 100644 (file)
@@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle)
 
        ring = &adev->uvd.ring;
        sprintf(ring->name, "uvd");
-       r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf,
-                            &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
+       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 
        return r;
 }
@@ -1002,7 +1001,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
        }
 }
 
-const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
+static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
        .name = "uvd_v6_0",
        .early_init = uvd_v6_0_early_init,
        .late_init = NULL,
@@ -1023,6 +1022,9 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
+       .type = AMDGPU_RING_TYPE_UVD,
+       .align_mask = 0xf,
+       .nop = PACKET0(mmUVD_NO_OP, 0),
        .get_rptr = uvd_v6_0_ring_get_rptr,
        .get_wptr = uvd_v6_0_ring_get_wptr,
        .set_wptr = uvd_v6_0_ring_set_wptr,
@@ -1046,6 +1048,9 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
+       .type = AMDGPU_RING_TYPE_UVD,
+       .align_mask = 0xf,
+       .nop = PACKET0(mmUVD_NO_OP, 0),
        .get_rptr = uvd_v6_0_ring_get_rptr,
        .get_wptr = uvd_v6_0_ring_get_wptr,
        .set_wptr = uvd_v6_0_ring_set_wptr,
@@ -1091,3 +1096,30 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
        adev->uvd.irq.num_types = 1;
        adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
 }
+
+const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
+{
+               .type = AMD_IP_BLOCK_TYPE_UVD,
+               .major = 6,
+               .minor = 0,
+               .rev = 0,
+               .funcs = &uvd_v6_0_ip_funcs,
+};
+
+const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
+{
+               .type = AMD_IP_BLOCK_TYPE_UVD,
+               .major = 6,
+               .minor = 2,
+               .rev = 0,
+               .funcs = &uvd_v6_0_ip_funcs,
+};
+
+const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
+{
+               .type = AMD_IP_BLOCK_TYPE_UVD,
+               .major = 6,
+               .minor = 3,
+               .rev = 0,
+               .funcs = &uvd_v6_0_ip_funcs,
+};