drm/amd: fix include notation and remove -Iinclude/drm flag

[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f41c1f24af9dd1ff49f36e0e84427233d56e6cf0..1da98e610e3762e0938400386bef1ade5375446e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -23,7 +23,7 @@
 #include <linux/firmware.h>
 #include <linux/slab.h>
 #include <linux/module.h>
-#include "drmP.h"
+#include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_atombios.h"
 #include "amdgpu_ih.h"
@@ -106,6 +106,8 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 
        if (adev->asic_type == CHIP_VEGA10)
                nbio_pcie_id = &nbio_v6_1_pcie_index_data;
+       else
+               BUG();
 
        address = nbio_pcie_id->index_offset;
        data = nbio_pcie_id->data_offset;
@@ -125,6 +127,8 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 
        if (adev->asic_type == CHIP_VEGA10)
                nbio_pcie_id = &nbio_v6_1_pcie_index_data;
+       else
+               BUG();
 
        address = nbio_pcie_id->index_offset;
        data = nbio_pcie_id->data_offset;
@@ -296,13 +300,9 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
        { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
        { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
        { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
        { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
        { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
        { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
-       { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
-       { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
 };
 
 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
@@ -322,6 +322,22 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
        return val;
 }
 
+static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+                                        bool indexed, u32 se_num,
+                                        u32 sh_num, u32 reg_offset)
+{
+       if (indexed) {
+               return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+       } else {
+               switch (reg_offset) {
+               case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
+                       return adev->gfx.config.gb_addr_config;
+               default:
+                       return RREG32(reg_offset);
+               }
+       }
+}
+
 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                            u32 sh_num, u32 reg_offset, u32 *value)
 {
@@ -345,10 +361,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                        if (reg_offset != asic_register_entry->reg_offset)
                                continue;
                        if (!asic_register_entry->untouched)
-                               *value = asic_register_entry->grbm_indexed ?
-                                       soc15_read_indexed_register(adev, se_num,
-                                                                sh_num, reg_offset) :
-                                       RREG32(reg_offset);
+                               *value = soc15_get_register_value(adev,
+                                                                 asic_register_entry->grbm_indexed,
+                                                                 se_num, sh_num, reg_offset);
                        return 0;
                }
        }
@@ -358,10 +373,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                        continue;
 
                if (!soc15_allowed_read_registers[i].untouched)
-                       *value = soc15_allowed_read_registers[i].grbm_indexed ?
-                               soc15_read_indexed_register(adev, se_num,
-                                                        sh_num, reg_offset) :
-                               RREG32(reg_offset);
+                       *value = soc15_get_register_value(adev,
+                                                         soc15_allowed_read_registers[i].grbm_indexed,
+                                                         se_num, sh_num, reg_offset);
                return 0;
        }
        return -EINVAL;
@@ -483,9 +497,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
-               if (!amdgpu_sriov_vf(adev))
+               if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
                        amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
-               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               if (!amdgpu_sriov_vf(adev))
+                       amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                        amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
                amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
@@ -548,6 +563,7 @@ static int soc15_common_early_init(void *handle)
 
        if (amdgpu_sriov_vf(adev)) {
                amdgpu_virt_init_setting(adev);
+               xgpu_ai_mailbox_set_irq_funcs(adev);
        }
 
        /*
@@ -600,8 +616,23 @@ static int soc15_common_early_init(void *handle)
        return 0;
 }
 
+static int soc15_common_late_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       if (amdgpu_sriov_vf(adev))
+               xgpu_ai_mailbox_get_irq(adev);
+
+       return 0;
+}
+
 static int soc15_common_sw_init(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       if (amdgpu_sriov_vf(adev))
+               xgpu_ai_mailbox_add_irq_id(adev);
+
        return 0;
 }
 
@@ -632,6 +663,8 @@ static int soc15_common_hw_fini(void *handle)
 
        /* disable the doorbell aperture */
        soc15_enable_doorbell_aperture(adev, false);
+       if (amdgpu_sriov_vf(adev))
+               xgpu_ai_mailbox_put_irq(adev);
 
        return 0;
 }
@@ -773,6 +806,9 @@ static int soc15_common_set_clockgating_state(void *handle,
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
        switch (adev->asic_type) {
        case CHIP_VEGA10:
                nbio_v6_1_update_medium_grain_clock_gating(adev,
@@ -842,7 +878,7 @@ static int soc15_common_set_powergating_state(void *handle,
 const struct amd_ip_funcs soc15_common_ip_funcs = {
        .name = "soc15_common",
        .early_init = soc15_common_early_init,
-       .late_init = NULL,
+       .late_init = soc15_common_late_init,
        .sw_init = soc15_common_sw_init,
        .sw_fini = soc15_common_sw_fini,
        .hw_init = soc15_common_hw_init,