drm/amdgpu: fix VM faults caused by vm_grab_id() v4

[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index f352d755968681aa03c29031cf8182d544aadde3..e4e4b2ac77b741c37bf3fc140b4476c14d546717 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -212,7 +212,7 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
                           struct amdgpu_ib *ib)
 {
-       u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
+       u32 extra_bits = ib->vm_id & 0xf;
        u32 next_rptr = ring->wptr + 5;
 
        while ((next_rptr & 7) != 4)
@@ -393,6 +393,9 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                cik_srbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
 
+               WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
+                      adev->gfx.config.gb_addr_config & 0x70);
+
                WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
                WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 
@@ -633,9 +636,8 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
        ib.ptr[3] = 1;
        ib.ptr[4] = 0xDEADBEEF;
        ib.length_dw = 5;
-       r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
-                                                AMDGPU_FENCE_OWNER_UNDEFINED,
-                                                &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+                              NULL, &f);
        if (r)
                goto err1;
 
@@ -1066,6 +1068,8 @@ static void cik_sdma_print_status(void *handle)
                         i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
                dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
                         i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
+               dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
+                        i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
                mutex_lock(&adev->srbm_mutex);
                for (j = 0; j < 16; j++) {
                        cik_srbm_select(adev, 0, 0, 0, j);
@@ -1372,9 +1376,14 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       unsigned i;
+
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
-               adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
-               adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
+               for (i = 0; i < adev->sdma.num_instances; i++)
+                       adev->vm_manager.vm_pte_rings[i] =
+                               &adev->sdma.instance[i].ring;
+
+               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
        }
 }