drm/amdgpu: use the new VM backend for PTEs

[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e8dcfd59fc93353468aaada4c42e6ab4ca6d85a5..520122be798b2615cbcaabc9c97d0029ba0915c8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -30,7 +30,6 @@
 #include <drm/gpu_scheduler.h>
 #include <drm/drm_file.h>
 #include <drm/ttm/ttm_bo_driver.h>
-#include <linux/chash.h>
 
 #include "amdgpu_sync.h"
 #include "amdgpu_ring.h"
@@ -140,7 +139,6 @@ struct amdgpu_vm_bo_base {
 
 struct amdgpu_vm_pt {
        struct amdgpu_vm_bo_base        base;
-       bool                            huge;
 
        /* array of page tables, one for each directory entry */
        struct amdgpu_vm_pt             *entries;
@@ -167,11 +165,6 @@ struct amdgpu_vm_pte_funcs {
                            uint32_t incr, uint64_t flags);
 };
 
-#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
-#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
-#define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)
-
-
 struct amdgpu_task_info {
        char    process_name[TASK_COMM_LEN];
        char    task_name[TASK_COMM_LEN];
@@ -179,11 +172,57 @@ struct amdgpu_task_info {
        pid_t   tgid;
 };
 
-#define AMDGPU_PAGEFAULT_HASH_BITS 8
-struct amdgpu_retryfault_hashtable {
-       DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
-       spinlock_t      lock;
-       int             count;
+/**
+ * struct amdgpu_vm_update_params
+ *
+ * Encapsulate some VM table update parameters to reduce
+ * the number of function parameters
+ *
+ */
+struct amdgpu_vm_update_params {
+
+       /**
+        * @adev: amdgpu device we do this update for
+        */
+       struct amdgpu_device *adev;
+
+       /**
+        * @vm: optional amdgpu_vm we do this update for
+        */
+       struct amdgpu_vm *vm;
+
+       /**
+        * @pages_addr:
+        *
+        * DMA addresses to use for mapping
+        */
+       dma_addr_t *pages_addr;
+
+       /**
+        * @job: job to used for hw submission
+        */
+       struct amdgpu_job *job;
+
+       /**
+        * @ib: indirect buffer to fill with commands
+        */
+       struct amdgpu_ib *ib;
+
+       /**
+        * @num_dw_left: number of dw left for the IB
+        */
+       unsigned int num_dw_left;
+};
+
+struct amdgpu_vm_update_funcs {
+
+       int (*prepare)(struct amdgpu_vm_update_params *p, void * owner,
+                      struct dma_fence *exclusive);
+       int (*update)(struct amdgpu_vm_update_params *p,
+                     struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
+                     unsigned count, uint32_t incr, uint64_t flags);
+       int (*commit)(struct amdgpu_vm_update_params *p,
+                     struct dma_fence **fence);
 };
 
 struct amdgpu_vm {
@@ -221,7 +260,10 @@ struct amdgpu_vm {
        struct amdgpu_vmid      *reserved_vmid[AMDGPU_MAX_VMHUBS];
 
        /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
-       bool                    use_cpu_for_update;
+       bool                                    use_cpu_for_update;
+
+       /* Functions to use for VM table updates */
+       const struct amdgpu_vm_update_funcs     *update_funcs;
 
        /* Flag to indicate ATS support from PTE for GFX9 */
        bool                    pte_support_ats;
@@ -245,7 +287,6 @@ struct amdgpu_vm {
        struct ttm_lru_bulk_move lru_bulk_move;
        /* mark whether can do the bulk move */
        bool                    bulk_moveable;
-       struct amdgpu_retryfault_hashtable *fault_hash;
 };
 
 struct amdgpu_vm_manager {
@@ -289,8 +330,13 @@ struct amdgpu_vm_manager {
 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
 
+extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
+extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
+
 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
+
+long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                   int vm_context, unsigned int pasid);
 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
@@ -303,9 +349,6 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm);
 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                              int (*callback)(void *p, struct amdgpu_bo *bo),
                              void *param);
-int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
-                       struct amdgpu_vm *vm,
-                       uint64_t saddr, uint64_t size);
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
                                 struct amdgpu_vm *vm);
@@ -319,6 +362,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
                        bool clear);
 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
                             struct amdgpu_bo *bo, bool evicted);
+uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
                                       struct amdgpu_bo *bo);
 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
@@ -358,9 +402,6 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
 
 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
                                struct amdgpu_vm *vm);
-
-int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
-
-void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
+void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
 
 #endif