Merge tag 'amd-drm-next-5.19-2022-04-15' of https://gitlab.freedesktop.org/agd5f...

[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index a025f080aa6a63df0b905082c7cf9059e4231d4d..ea92edcc04320aac4c79a3e4162bdb8b62b48096 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -23,6 +23,10 @@
 
 #include <linux/module.h>
 
+#ifdef CONFIG_X86
+#include <asm/hypervisor.h>
+#endif
+
 #include <drm/drm_drv.h>
 
 #include "amdgpu.h"
@@ -723,8 +727,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
                        break;
                case CHIP_VEGA10:
                        soc15_set_virt_ops(adev);
-                       /* send a dummy GPU_INIT_DATA request to host on vega10 */
-                       amdgpu_virt_request_init_data(adev);
+#ifdef CONFIG_X86
+                       /* not send GPU_INIT_DATA with MS_HYPERV*/
+                       if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
+#endif
+                               /* send a dummy GPU_INIT_DATA request to host on vega10 */
+                               amdgpu_virt_request_init_data(adev);
                        break;
                case CHIP_VEGA20:
                case CHIP_ARCTURUS:
@@ -862,11 +870,11 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
        uint32_t timeout = 50000;
        uint32_t i, tmp;
        uint32_t ret = 0;
-       static void *scratch_reg0;
-       static void *scratch_reg1;
-       static void *scratch_reg2;
-       static void *scratch_reg3;
-       static void *spare_int;
+       void *scratch_reg0;
+       void *scratch_reg1;
+       void *scratch_reg2;
+       void *scratch_reg3;
+       void *spare_int;
 
        if (!adev->gfx.rlc.rlcg_reg_access_supported) {
                dev_err(adev->dev,
@@ -919,7 +927,7 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
                                                "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
                                } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
                                        dev_err(adev->dev,
-                                               "regiser is not in range, rlcg failed to program reg: 0x%05x\n", offset);
+                                               "register is not in range, rlcg failed to program reg: 0x%05x\n", offset);
                                } else {
                                        dev_err(adev->dev,
                                                "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);