drm/amd: Move helper for dynamic speed switch check out of smu13

[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e25f085ee8867419605bcbe74f8ab869bf72b526..a2cdde0ca0a72f42ef7cc4e2929fda910c066548 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1458,6 +1458,25 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
        return true;
 }
 
+/*
+ * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
+ * speed switching. Until we have confirmation from Intel that a specific host
+ * supports it, it's safer that we keep it disabled for all.
+ *
+ * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
+ * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
+ */
+bool amdgpu_device_pcie_dynamic_switching_supported(void)
+{
+#if IS_ENABLED(CONFIG_X86)
+       struct cpuinfo_x86 *c = &cpu_data(0);
+
+       if (c->x86_vendor == X86_VENDOR_INTEL)
+               return false;
+#endif
+       return true;
+}
+
 /**
  * amdgpu_device_should_use_aspm - check if the device should program ASPM
  *
@@ -2552,7 +2571,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                        adev->ip_blocks[i].status.hw = true;
 
                        /* right after GMC hw init, we create CSA */
-                       if (amdgpu_mcbp) {
+                       if (adev->gfx.mcbp) {
                                r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
                                                               AMDGPU_GEM_DOMAIN_VRAM |
                                                               AMDGPU_GEM_DOMAIN_GTT,
@@ -3673,6 +3692,23 @@ static const struct attribute *amdgpu_dev_attributes[] = {
        NULL
 };
 
+static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
+{
+       if (amdgpu_mcbp == 1)
+               adev->gfx.mcbp = true;
+
+       if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
+           (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
+           adev->gfx.num_gfx_rings)
+               adev->gfx.mcbp = true;
+
+       if (amdgpu_sriov_vf(adev))
+               adev->gfx.mcbp = true;
+
+       if (adev->gfx.mcbp)
+               DRM_INFO("MCBP is enabled\n");
+}
+
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -3824,9 +3860,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
        DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
 
-       if (amdgpu_mcbp)
-               DRM_INFO("MCBP is enabled\n");
-
        /*
         * Reset domain needs to be present early, before XGMI hive discovered
         * (if any) and intitialized to use reset sem and in_gpu reset flag
@@ -3852,6 +3885,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        if (r)
                return r;
 
+       amdgpu_device_set_mcbp(adev);
+
        /* Get rid of things like offb */
        r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
        if (r)
@@ -4018,6 +4053,11 @@ fence_driver_init:
        /* Get a log2 for easy divisions. */
        adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
 
+       r = amdgpu_atombios_sysfs_init(adev);
+       if (r)
+               drm_err(&adev->ddev,
+                       "registering atombios sysfs failed (%d).\n", r);
+
        r = amdgpu_pm_sysfs_init(adev);
        if (r)
                DRM_ERROR("registering pm sysfs failed (%d).\n", r);