int active_events;
int burst_len;
int buswidth[DMC_MAX_CHANNELS];
+ int ddrmon_stride;
};
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
if (!(dfi->channel_mask & BIT(i)))
continue;
res->c[i].read_access = readl_relaxed(dfi_regs +
- DDRMON_CH0_RD_NUM + i * 20);
+ DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
res->c[i].write_access = readl_relaxed(dfi_regs +
- DDRMON_CH0_WR_NUM + i * 20);
+ DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
res->c[i].access = readl_relaxed(dfi_regs +
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride);
res->c[i].clock_cycles = readl_relaxed(dfi_regs +
- DDRMON_CH0_COUNT_NUM + i * 20);
+ DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
}
}
dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+ dfi->ddrmon_stride = 0x14;
+
return 0;
};
dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+ dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single channel on this SoC */
+
return 0;
};