hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
- return ((cycle_t)hi << 32) | lo;
+ return ((u64)hi << 32) | lo;
}
/**
return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
}
-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static u64 exynos4_frc_read(struct clocksource *cs)
{
return exynos4_read_count_32();
}
static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
{
unsigned int tcon;
- cycle_t comp_cycle;
+ u64 comp_cycle;
tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);