Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk...

[linux-2.6-block.git] / drivers / clk / qcom / gcc-sdm845.c

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index e78e6f5b99fcc1b700372674bebfd7b909a2bce6..fa1a196350f1542ab5acf95528b7b329ecaddb98 100644 (file)
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -25,8 +25,6 @@
 #include "gdsc.h"
 #include "reset.h"
 
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
        P_BI_TCXO,
        P_AUD_REF_CLK,
@@ -1103,6 +1101,7 @@ static struct clk_branch gcc_camera_ahb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_camera_ahb_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1129,6 +1128,7 @@ static struct clk_branch gcc_camera_xo_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_camera_xo_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1270,6 +1270,7 @@ static struct clk_branch gcc_disp_ahb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_disp_ahb_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1328,6 +1329,7 @@ static struct clk_branch gcc_disp_xo_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_disp_xo_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1397,6 +1399,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_gpu_cfg_ahb_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2985,6 +2988,7 @@ static struct clk_branch gcc_video_ahb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_video_ahb_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -3011,6 +3015,7 @@ static struct clk_branch gcc_video_xo_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_video_xo_clk",
+                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -3049,6 +3054,36 @@ static struct clk_branch gcc_vs_ctrl_clk = {
        },
 };
 
+static struct clk_branch gcc_cpuss_dvm_bus_clk = {
+       .halt_reg = 0x48190,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x48190,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_cpuss_dvm_bus_clk",
+                       .flags = CLK_IS_CRITICAL,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_cpuss_gnoc_clk = {
+       .halt_reg = 0x48004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x48004,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(22),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_cpuss_gnoc_clk",
+                       .flags = CLK_IS_CRITICAL,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct gdsc pcie_0_gdsc = {
        .gdscr = 0x6b004,
        .pd = {
@@ -3344,6 +3379,8 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
        [GPLL0] = &gpll0.clkr,
        [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
        [GPLL4] = &gpll4.clkr,
+       [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
+       [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_sdm845_resets[] = {
@@ -3433,10 +3470,6 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
        regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
        regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
 
-       /* Enable CPUSS clocks */
-       regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
-       regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
-
        return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
 }