Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and...

[linux-2.6-block.git] / drivers / clk / clk-fractional-divider.c

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index fdf625fb10faa03fc8c394555612fdcdf855ac09..545dceec0bbf0230f72163a1d0506f1dc8401b49 100644 (file)
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2014 Intel Corporation
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
  * Adjustable fractional divider clock implementation.
  * Output rate = (m / n) * parent_rate.
  * Uses rational best approximation algorithm.
@@ -40,6 +37,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
        m = (val & fd->mmask) >> fd->mshift;
        n = (val & fd->nmask) >> fd->nshift;
 
+       if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+               m++;
+               n++;
+       }
+
        if (!n || !m)
                return parent_rate;
 
@@ -103,6 +105,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
                        GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
                        &m, &n);
 
+       if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+               m--;
+               n--;
+       }
+
        if (fd->lock)
                spin_lock_irqsave(fd->lock, flags);
        else