* Represents an NVM Express device. Each nvme_dev is a PCI function.
*/
struct nvme_dev {
- struct list_head node;
struct nvme_queue **queues;
u32 __iomem *dbs;
struct pci_dev *pci_dev;
struct msix_entry *entry;
struct nvme_bar __iomem *bar;
struct list_head namespaces;
+ char serial[20];
+ char model[40];
+ char firmware_rev[8];
};
/*
int result;
struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
+ if (!nvmeq)
+ return NULL;
+
result = adapter_alloc_cq(dev, qid, nvmeq);
if (result < 0)
goto free_nvmeq;
dev->dbs = ((void __iomem *)dev->bar) + 4096;
nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
+ if (!nvmeq)
+ return -ENOMEM;
aqa = nvmeq->q_depth - 1;
aqa |= aqa << 16;
{
int res, nn, i;
struct nvme_ns *ns, *next;
+ struct nvme_id_ctrl *ctrl;
void *id;
dma_addr_t dma_addr;
struct nvme_command cid, crt;
goto out_free;
}
- nn = le32_to_cpup(&((struct nvme_id_ctrl *)id)->nn);
+ ctrl = id;
+ nn = le32_to_cpup(&ctrl->nn);
+ memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
+ memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
+ memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
cid.identify.cns = 0;
memset(&crt, 0, sizeof(crt));