Merge branch 'x86/cache' into perf/core, to pick up fixes

[linux-2.6-block.git] / arch / x86 / kernel / cpu / intel_rdt_pseudo_lock.c

diff --git a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
index 966ac0c20d671a0f9b9b264874840bbdbed374bb..815b4e92522ccfffb2864bddb4d67e6efa6e887b 100644 (file)
--- a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
+++ b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
@@ -93,7 +93,7 @@ static u64 get_prefetch_disable_bits(void)
                 */
                return 0xF;
        case INTEL_FAM6_ATOM_GOLDMONT:
-       case INTEL_FAM6_ATOM_GEMINI_LAKE:
+       case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
                /*
                 * SDM defines bits of MSR_MISC_FEATURE_CONTROL register
                 * as:
@@ -1070,7 +1070,7 @@ static int measure_l2_residency(void *_plr)
         */
        switch (boot_cpu_data.x86_model) {
        case INTEL_FAM6_ATOM_GOLDMONT:
-       case INTEL_FAM6_ATOM_GEMINI_LAKE:
+       case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
                perf_miss_attr.config = X86_CONFIG(.event = 0xd1,
                                                   .umask = 0x10);
                perf_hit_attr.config = X86_CONFIG(.event = 0xd1,