RISC-V: KVM: Expose Zicboz to the guest

[linux-2.6-block.git] / arch / riscv / kvm / vcpu.c

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0a875ebe11afa00b8f29f372e130e..6adb1b6112a1d0dfe90e064ca4e5631530fc4580 100644 (file)
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
        KVM_ISA_EXT_ARR(SVPBMT),
        KVM_ISA_EXT_ARR(ZIHINTPAUSE),
        KVM_ISA_EXT_ARR(ZICBOM),
+       KVM_ISA_EXT_ARR(ZICBOZ),
 };
 
 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -138,6 +139,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
        WRITE_ONCE(vcpu->arch.irqs_pending, 0);
        WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
 
+       kvm_riscv_vcpu_pmu_reset(vcpu);
+
        vcpu->arch.hfence_head = 0;
        vcpu->arch.hfence_tail = 0;
        memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue));
@@ -194,6 +197,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
        /* Setup VCPU timer */
        kvm_riscv_vcpu_timer_init(vcpu);
 
+       /* setup performance monitoring */
+       kvm_riscv_vcpu_pmu_init(vcpu);
+
        /* Reset VCPU */
        kvm_riscv_reset_vcpu(vcpu);
 
@@ -216,6 +222,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
        /* Cleanup VCPU timer */
        kvm_riscv_vcpu_timer_deinit(vcpu);
 
+       kvm_riscv_vcpu_pmu_deinit(vcpu);
+
        /* Free unused pages pre-allocated for G-stage page table mappings */
        kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
 }
@@ -276,6 +284,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
                        return -EINVAL;
                reg_val = riscv_cbom_block_size;
                break;
+       case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+               if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
+                       return -EINVAL;
+               reg_val = riscv_cboz_block_size;
+               break;
        case KVM_REG_RISCV_CONFIG_REG(mvendorid):
                reg_val = vcpu->arch.mvendorid;
                break;
@@ -347,6 +360,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
                break;
        case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
                return -EOPNOTSUPP;
+       case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+               return -EOPNOTSUPP;
        case KVM_REG_RISCV_CONFIG_REG(mvendorid):
                if (!vcpu->arch.ran_atleast_once)
                        vcpu->arch.mvendorid = reg_val;
@@ -858,6 +873,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
        if (riscv_isa_extension_available(isa, ZICBOM))
                henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
 
+       if (riscv_isa_extension_available(isa, ZICBOZ))
+               henvcfg |= ENVCFG_CBZE;
+
        csr_write(CSR_HENVCFG, henvcfg);
 #ifdef CONFIG_32BIT
        csr_write(CSR_HENVCFGH, henvcfg >> 32);