Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"

[linux-block.git] / arch / riscv / include / asm / vdso / processor.h

diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
index fa70cfe507aa118260d1d751cc1b7658fa739349..14f5d27783b85811a4f7e6e1d43c9b5ee9aca5a1 100644 (file)
--- a/arch/riscv/include/asm/vdso/processor.h
+++ b/arch/riscv/include/asm/vdso/processor.h
@@ -4,30 +4,26 @@
 
 #ifndef __ASSEMBLY__
 
-#include <linux/jump_label.h>
 #include <asm/barrier.h>
-#include <asm/hwcap.h>
 
 static inline void cpu_relax(void)
 {
-       if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
 #ifdef __riscv_muldiv
-               int dummy;
-               /* In lieu of a halt instruction, induce a long-latency stall. */
-               __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
+       int dummy;
+       /* In lieu of a halt instruction, induce a long-latency stall. */
+       __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
 #endif
-       } else {
-               /*
-                * Reduce instruction retirement.
-                * This assumes the PC changes.
-                */
-#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
-               __asm__ __volatile__ ("pause");
+
+#ifdef __riscv_zihintpause
+       /*
+        * Reduce instruction retirement.
+        * This assumes the PC changes.
+        */
+       __asm__ __volatile__ ("pause");
 #else
-               /* Encoding of the pause instruction */
-               __asm__ __volatile__ (".4byte 0x100000F");
+       /* Encoding of the pause instruction */
+       __asm__ __volatile__ (".4byte 0x100000F");
 #endif
-       }
        barrier();
 }