powerpc/booke64: Critical and machine check exception support

[linux-2.6-block.git] / arch / powerpc / mm / tlb_nohash.c

diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index b37a58e1c92da8bfa9092828f6d3a92126da29d9..ae3d5b799b9004f3089176c90a22b4dd8e76c84a 100644 (file)
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -144,6 +144,15 @@ int mmu_vmemmap_psize;             /* Page size used for the virtual mem map */
 int book3e_htw_mode;           /* HW tablewalk?  Value is PPC_HTW_* */
 unsigned long linear_map_top;  /* Top of linear mapping */
 
+
+/*
+ * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
+ * exceptions.  This is used for bolted and e6500 TLB miss handlers which
+ * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
+ * this is set to zero.
+ */
+int extlb_level_exc;
+
 #endif /* CONFIG_PPC64 */
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
@@ -559,6 +568,7 @@ static void setup_mmu_htw(void)
                break;
 #ifdef CONFIG_PPC_FSL_BOOK3E
        case PPC_HTW_E6500:
+               extlb_level_exc = EX_TLB_SIZE;
                patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
                patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
                break;
@@ -652,6 +662,7 @@ static void __early_init_mmu(int boot_cpu)
                memblock_enforce_memory_limit(linear_map_top);
 
                if (book3e_htw_mode == PPC_HTW_NONE) {
+                       extlb_level_exc = EX_TLB_SIZE;
                        patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
                        patch_exception(0x1e0,
                                exc_instruction_tlb_miss_bolted_book3e);