powerpc: convert to use __HEAD and HEAD_TEXT macros.

[linux-block.git] / arch / powerpc / kernel / head_8xx.S

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 96cea8e753c4ff71b0b2b80d535d3ffe24ebd6c5..52ff8c53b93c0da349fb3f126e61a39fdfa8eec6 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -19,6 +19,7 @@
  *
  */
 
+#include <linux/init.h>
 #include <asm/processor.h>
 #include <asm/page.h>
 #include <asm/mmu.h>
@@ -38,7 +39,7 @@
 #else
 #define DO_8xx_CPU6(val, reg)
 #endif
-       .section        .text.head, "ax"
+       __HEAD
 _ENTRY(_stext);
 _ENTRY(_start);
 
@@ -298,6 +299,12 @@ InstructionTLBMiss:
        stw     r10, 0(r0)
        stw     r11, 4(r0)
        mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
+#ifdef CONFIG_8xx_CPU15
+       addi    r11, r10, 0x1000
+       tlbie   r11
+       addi    r11, r10, -0x1000
+       tlbie   r11
+#endif
        DO_8xx_CPU6(0x3780, r3)
        mtspr   SPRN_MD_EPN, r10        /* Have to use MD_EPN for walk, MI_EPN can't */
        mfspr   r10, SPRN_M_TWB /* Get level 1 table entry address */
@@ -326,8 +333,18 @@ InstructionTLBMiss:
        mfspr   r11, SPRN_MD_TWC        /* ....and get the pte address */
        lwz     r10, 0(r11)     /* Get the pte */
 
+#ifdef CONFIG_SWAP
+       /* do not set the _PAGE_ACCESSED bit of a non-present page */
+       andi.   r11, r10, _PAGE_PRESENT
+       beq     4f
+       ori     r10, r10, _PAGE_ACCESSED
+       mfspr   r11, SPRN_MD_TWC        /* get the pte address again */
+       stw     r10, 0(r11)
+4:
+#else
        ori     r10, r10, _PAGE_ACCESSED
        stw     r10, 0(r11)
+#endif
 
        /* The Linux PTE won't go exactly into the MMU TLB.
         * Software indicator bits 21, 22 and 28 must be clear.
@@ -392,8 +409,17 @@ DataStoreTLBMiss:
        DO_8xx_CPU6(0x3b80, r3)
        mtspr   SPRN_MD_TWC, r11
 
-       mfspr   r11, SPRN_MD_TWC        /* get the pte address again */
+#ifdef CONFIG_SWAP
+       /* do not set the _PAGE_ACCESSED bit of a non-present page */
+       andi.   r11, r10, _PAGE_PRESENT
+       beq     4f
+       ori     r10, r10, _PAGE_ACCESSED
+4:
+       /* and update pte in table */
+#else
        ori     r10, r10, _PAGE_ACCESSED
+#endif
+       mfspr   r11, SPRN_MD_TWC        /* get the pte address again */
        stw     r10, 0(r11)
 
        /* The Linux PTE won't go exactly into the MMU TLB.
@@ -501,7 +527,16 @@ DataTLBError:
 
        /* Update 'changed', among others.
        */
+#ifdef CONFIG_SWAP
+       ori     r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
+       /* do not set the _PAGE_ACCESSED bit of a non-present page */
+       andi.   r11, r10, _PAGE_PRESENT
+       beq     4f
+       ori     r10, r10, _PAGE_ACCESSED
+4:
+#else
        ori     r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
+#endif
        mfspr   r11, SPRN_MD_TWC                /* Get pte address again */
        stw     r10, 0(r11)             /* and update pte in table */
 
@@ -727,13 +762,13 @@ initial_mmu:
        mtspr   SPRN_MD_TWC, r9
        li      r11, MI_BOOTINIT        /* Create RPN for address 0 */
        addis   r11, r11, 0x0080        /* Add 8M */
-       mtspr   SPRN_MD_RPN, r8
+       mtspr   SPRN_MD_RPN, r11
 
        addis   r8, r8, 0x0080          /* Add 8M */
        mtspr   SPRN_MD_EPN, r8
        mtspr   SPRN_MD_TWC, r9
        addis   r11, r11, 0x0080        /* Add 8M */
-       mtspr   SPRN_MD_RPN, r8
+       mtspr   SPRN_MD_RPN, r11
 #endif
 
        /* Since the cache is enabled according to the information we