powerpc/mm: Add support for handling > 512TB address in SLB miss

[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / hash-64k.h

diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 3bcf269f8f55470097ac56680685321bf13e62ba..f7a4f5cbf63e8284d658f2fdad5faf26924a7301 100644 (file)
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -7,6 +7,12 @@
 #define H_PUD_INDEX_SIZE  7
 #define H_PGD_INDEX_SIZE  8
 
+/*
+ * Each context is 512TB size. SLB miss for first context/default context
+ * is handled in the hotpath.
+ */
+#define MAX_EA_BITS_PER_CONTEXT                49
+
 /*
  * 64k aligned address free up few of the lower bits of RPN for us
  * We steal that here. For more deatils look at pte_pfn/pfn_pte()
@@ -16,6 +22,13 @@
 #define H_PAGE_BUSY    _RPAGE_RPN44     /* software: PTE & hash are busy */
 #define H_PAGE_HASHPTE _RPAGE_RPN43    /* PTE has associated HPTE */
 
+/* memory key bits. */
+#define H_PTE_PKEY_BIT0        _RPAGE_RSV1
+#define H_PTE_PKEY_BIT1        _RPAGE_RSV2
+#define H_PTE_PKEY_BIT2        _RPAGE_RSV3
+#define H_PTE_PKEY_BIT3        _RPAGE_RSV4
+#define H_PTE_PKEY_BIT4        _RPAGE_RSV5
+
 /*
  * We need to differentiate between explicit huge page and THP huge
  * page, since THP huge page also need to track real subpage details