source "init/Kconfig"
+config CPU_MIPS32
+ bool
+ default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+
+config CPU_MIPS64
+ bool
+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
+config CPU_MIPSR1
+ bool
+ default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
+
+config CPU_MIPSR2
+ bool
+ default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
+
config SYS_SUPPORTS_32BIT_KERNEL
bool
config SYS_SUPPORTS_64BIT_KERNEL
The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC.
Please refer to <http://www.tanbac.co.jp/> about Mbase.
+config TANBAC_TB0287
+ bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
+ depends on TANBAC_TB022X
+ help
+ The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC.
+ Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
+
config VICTOR_MPC30X
bool "Support for Victor MP-C303/304"
depends on MACH_VR41XX
bool "Support for DECstations"
select BOOT_ELF32
select DMA_NONCOHERENT
+ select EARLY_PRINTK
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)"
depends on EXPERIMENTAL
select DMA_NONCOHERENT
+ select IRQ_CPU
select HW_HAS_PCI
select MIPS_GT64120
select SYS_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_GT64120
+ select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
help
- This enables support for the QED R5231-based MIPS Atlas evaluation
+ This enables support for the MIPS Technologies Atlas evaluation
board.
config MIPS_MALTA
select BOOT_ELF32
select HAVE_STD_PC_SERIAL_PORT
select DMA_NONCOHERENT
+ select IRQ_CPU
select GENERIC_ISA_DMA
select HW_HAS_PCI
select I8259
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
help
- This enables support for the VR5000-based MIPS Malta evaluation
+ This enables support for the MIPS Technologies Malta evaluation
board.
config MIPS_SEAD
select DMA_NONCOHERENT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
+ help
+ This enables support for the MIPS Technologies SEAD evaluation
+ board.
config MOMENCO_OCELOT
bool "Support for Momentum Ocelot board"
bool "Hypertransport Support for PMC-Sierra Yosemite"
depends on PMC_YOSEMITE
+config PNX8550_V2PCI
+ bool "Support for Philips PNX8550 based Viper2-PCI board"
+ select PNX8550
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
+config PNX8550_JBS
+ bool "Support for Philips PNX8550 based JBS board"
+ select PNX8550
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
config DDB5074
bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
depends on EXPERIMENTAL
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
help
Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the
select OWN_DMA
select DMA_IP32
select DMA_NONCOHERENT
+ select HAS_TXX9_SERIAL
select HW_HAS_PCI
select R5000_CPU_SCACHE
select RM7000_CPU_SCACHE
help
If you want this kernel to run on SGI O2 workstation, say Y here.
+config SOC_AU1200
+ bool
+ select SOC_AU1X00
+
config SOC_AU1X00
bool "Support for AMD/Alchemy Au1X00 SOCs"
select SYS_SUPPORTS_32BIT_KERNEL
config SOC_AU1550
bool "SOC_AU1550"
+config TOSHIBA_RBTX4938
+ bool "Support for Toshiba RBTX4938 board"
+ select HAVE_STD_PC_SERIAL_PORT
+ select DMA_NONCOHERENT
+ select GENERIC_ISA_DMA
+ select HAS_TXX9_SERIAL
+ select HW_HAS_PCI
+ select I8259
+ select ISA
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select TOSHIBA_BOARDS
+ help
+ This Toshiba board is based on the TX4938 processor. Say Y here to
+ support this machine type
+
endchoice
choice
config MIPS_PB1500
bool "PB1500 board"
depends on SOC_AU1500
- select DMA_COHERENT
+ select DMA_NONCOHERENT
select HW_HAS_PCI
config MIPS_PB1550
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
+config MIPS_PB1200
+ bool "AMD Alchemy PB1200 board"
+ select SOC_AU1200
+ select DMA_NONCOHERENT
+ select MIPS_DISABLE_OBSOLETE_IDE
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
config MIPS_DB1000
bool "DB1000 board"
depends on SOC_AU1000
config MIPS_DB1500
bool "DB1500 board"
depends on SOC_AU1500
- select DMA_COHERENT
+ select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
bool "DB1550 board"
depends on SOC_AU1550
select HW_HAS_PCI
- select DMA_COHERENT
+ select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
config MIPS_BOSPORUS
depends on SOC_AU1500
select DMA_NONCOHERENT
+config MIPS_DB1200
+ bool "AMD Alchemy DB1200 board"
+ select SOC_AU1200
+ select DMA_NONCOHERENT
+ select MIPS_DISABLE_OBSOLETE_IDE
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
config MIPS_MIRAGE
bool "Mirage board"
depends on SOC_AU1500
endchoice
-config SIBYTE_SB1xxx_SOC
- bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
- depends on EXPERIMENTAL
- select BOOT_ELF32
- select DMA_COHERENT
- select SWAP_IO_SPACE
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
-
-choice
- prompt "BCM1xxx SOC-based board"
- depends on SIBYTE_SB1xxx_SOC
- default SIBYTE_SWARM
- help
- Enable support for boards based on the SiByte line of SOCs
- from Broadcom. There are configurations for the known
- evaluation boards, or you can choose "Other" and add your
- own board support code.
-
-config SIBYTE_SWARM
- bool "BCM91250A-SWARM"
- select SIBYTE_SB1250
-
-config SIBYTE_SENTOSA
- bool "BCM91250E-Sentosa"
- select SIBYTE_SB1250
-
-config SIBYTE_RHONE
- bool "BCM91125E-Rhone"
- select SIBYTE_BCM1125H
-
-config SIBYTE_CARMEL
- bool "BCM91120x-Carmel"
- select SIBYTE_BCM1120
-
-config SIBYTE_PTSWARM
- bool "BCM91250PT-PTSWARM"
- select SIBYTE_SB1250
-
-config SIBYTE_LITTLESUR
- bool "BCM91250C2-LittleSur"
- select SIBYTE_SB1250
-
-config SIBYTE_CRHINE
- bool "BCM91120C-CRhine"
- select SIBYTE_BCM1120
-
-config SIBYTE_CRHONE
- bool "BCM91125C-CRhone"
- select SIBYTE_BCM1125
-
-config SIBYTE_UNKNOWN
- bool "Other"
-
-endchoice
-
-config SIBYTE_BOARD
- bool
- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
- default y
-
-choice
- prompt "BCM1xxx SOC Type"
- depends on SIBYTE_UNKNOWN
- default SIBYTE_UNK_BCM1250
- help
- Since you haven't chosen a known evaluation board from
- Broadcom, you must explicitly pick the SOC this kernel is
- targetted for.
-
-config SIBYTE_UNK_BCM1250
- bool "BCM1250"
- select SIBYTE_SB1250
-
-config SIBYTE_UNK_BCM1120
- bool "BCM1120"
- select SIBYTE_BCM1120
-
-config SIBYTE_UNK_BCM1125
- bool "BCM1125"
- select SIBYTE_BCM1125
-
-config SIBYTE_UNK_BCM1125H
- bool "BCM1125H"
- select SIBYTE_BCM1125H
-
-endchoice
-
-config SIBYTE_SB1250
- bool
- select HW_HAS_PCI
-
-config SIBYTE_BCM1120
- bool
- select SIBYTE_BCM112X
-
-config SIBYTE_BCM1125
- bool
- select HW_HAS_PCI
- select SIBYTE_BCM112X
-
-config SIBYTE_BCM1125H
- bool
- select HW_HAS_PCI
- select SIBYTE_BCM112X
-
-config SIBYTE_BCM112X
- bool
-
-choice
- prompt "SiByte SOC Stepping"
- depends on SIBYTE_SB1xxx_SOC
-
-config CPU_SB1_PASS_1
- bool "1250 Pass1"
- depends on SIBYTE_SB1250
- select CPU_HAS_PREFETCH
-
-config CPU_SB1_PASS_2_1250
- bool "1250 An"
- depends on SIBYTE_SB1250
- select CPU_SB1_PASS_2
- help
- Also called BCM1250 Pass 2
-
-config CPU_SB1_PASS_2_2
- bool "1250 Bn"
- depends on SIBYTE_SB1250
- select CPU_HAS_PREFETCH
- help
- Also called BCM1250 Pass 2.2
-
-config CPU_SB1_PASS_4
- bool "1250 Cn"
- depends on SIBYTE_SB1250
- select CPU_HAS_PREFETCH
- help
- Also called BCM1250 Pass 3
-
-config CPU_SB1_PASS_2_112x
- bool "112x Hybrid"
- depends on SIBYTE_BCM112X
- select CPU_SB1_PASS_2
-
-config CPU_SB1_PASS_3
- bool "112x An"
- depends on SIBYTE_BCM112X
- select CPU_HAS_PREFETCH
-
-endchoice
-
-config CPU_SB1_PASS_2
- bool
-
-config SIBYTE_HAS_LDT
- bool
- depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
- default y
-
-config SIMULATION
- bool "Running under simulation"
- depends on SIBYTE_SB1xxx_SOC
- help
- Build a kernel suitable for running under the GDB simulator.
- Primarily adjusts the kernel's notion of time.
-
-config SIBYTE_CFE
- bool "Booting from CFE"
- depends on SIBYTE_SB1xxx_SOC
- help
- Make use of the CFE API for enumerating available memory,
- controlling secondary CPUs, and possibly console output.
-
-config SIBYTE_CFE_CONSOLE
- bool "Use firmware console"
- depends on SIBYTE_CFE
- help
- Use the CFE API's console write routines during boot. Other console
- options (VT console, sb1250 duart console, etc.) should not be
- configured.
-
-config SIBYTE_STANDALONE
- bool
- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
- default y
-
-config SIBYTE_STANDALONE_RAM_SIZE
- int "Memory size (in megabytes)"
- depends on SIBYTE_STANDALONE
- default "32"
-
-config SIBYTE_BUS_WATCHER
- bool "Support for Bus Watcher statistics"
- depends on SIBYTE_SB1xxx_SOC
- help
- Handle and keep statistics on the bus error interrupts (COR_ECC,
- BAD_ECC, IO_BUS).
-
-config SIBYTE_BW_TRACE
- bool "Capture bus trace before bus error"
- depends on SIBYTE_BUS_WATCHER
- help
- Run a continuous bus trace, dumping the raw data as soon as
- a ZBbus error is detected. Cannot work if ZBbus profiling
- is turned on, and also will interfere with JTAG-based trace
- buffer activity. Raw buffer data is dumped to console, and
- must be processed off-line.
-
-config SIBYTE_SB1250_PROF
- bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
- depends on SIBYTE_SB1xxx_SOC
-
-config SIBYTE_TBPROF
- bool "Support for ZBbus profiling"
- depends on SIBYTE_SB1xxx_SOC
-
config SNI_RM200_PCI
bool "Support for SNI RM200 PCI"
select ARC
select ISA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_HIGHMEM
help
The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
Nixdorf Informationssysteme (SNI), parent company of Pyramid
bool "FPCIB0 Backplane Support"
depends on TOSHIBA_RBTX4927
+source "arch/mips/sgi-ip27/Kconfig"
+source "arch/mips/sibyte/Kconfig"
+source "arch/mips/tx4938/Kconfig"
+source "arch/mips/philips/pnx8550/common/Kconfig"
+
config RWSEM_GENERIC_SPINLOCK
bool
default y
config RWSEM_XCHGADD_ALGORITHM
bool
+ select HAS_TXX9_SERIAL
config GENERIC_CALIBRATE_DELAY
bool
default y
-config HAVE_DEC_LOCK
- bool
- default y
-
#
# Select some configuration options automatically based on user selections.
#
config LIMITED_DMA
bool
select HIGHMEM
+ select SYS_SUPPORTS_HIGHMEM
config MIPS_BONITO64
bool
depends on MIPS_IVR || MIPS_ITE8172
default y
+config PNX8550
+ bool
+ select SOC_PNX8550
+
+config SOC_PNX8550
+ bool
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+
config SWAP_IO_SPACE
bool
# depends on SGI_IP27
# default y
-config QL_ISP_A64
- bool
- depends on SGI_IP27
- default y
-
config TOSHIBA_BOARDS
bool
depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
prompt "CPU type"
default CPU_R4X00
-config CPU_MIPS32
- bool "MIPS32"
+config CPU_MIPS32_R1
+ bool "MIPS32 Release 1"
+ select CPU_HAS_PREFETCH
+ select CPU_SUPPORTS_32BIT_KERNEL
+ help
+ Choose this option to build a kernel for release 2 or later of the
+ MIPS32 architecture. Most modern embedded systems with a 32-bit
+ MIPS processor are based on a MIPS32 processor. If you know the
+ specific type of processor in your system, choose those that one
+ otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
+ Release 2 of the MIPS32 architecture is available since several
+ years so chances are you even have a MIPS32 Release 2 processor
+ in which case you should choose CPU_MIPS32_R2 instead for better
+ performance.
+
+config CPU_MIPS32_R2
+ bool "MIPS32 Release 2"
+ select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
+ help
+ Choose this option to build a kernel for release 1 or later of the
+ MIPS32 architecture. Most modern embedded systems with a 32-bit
+ MIPS processor are based on a MIPS32 processor. If you know the
+ specific type of processor in your system, choose those that one
+ otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
-config CPU_MIPS64
- bool "MIPS64"
+config CPU_MIPS64_R1
+ bool "MIPS64 Release 1"
+ select CPU_HAS_PREFETCH
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
+ help
+ Choose this option to build a kernel for release 1 or later of the
+ MIPS64 architecture. Many modern embedded systems with a 64-bit
+ MIPS processor are based on a MIPS64 processor. If you know the
+ specific type of processor in your system, choose those that one
+ otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
+ Release 2 of the MIPS64 architecture is available since several
+ years so chances are you even have a MIPS64 Release 2 processor
+ in which case you should choose CPU_MIPS64_R2 instead for better
+ performance.
+
+config CPU_MIPS64_R2
+ bool "MIPS64 Release 2"
+ select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
+ help
+ Choose this option to build a kernel for release 2 or later of the
+ MIPS64 architecture. Many modern embedded systems with a 64-bit
+ MIPS processor are based on a MIPS64 processor. If you know the
+ specific type of processor in your system, choose those that one
+ otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
config CPU_R3000
bool "R3000"
select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
help
Please make sure to pick the right CPU type. Linux/MIPS is not
designed to be generic, i.e. Kernels compiled for R3000 CPUs will
bool "R10000"
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
help
MIPS Technologies R10000-series processors.
bool "RM7000"
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
config CPU_RM9000
bool "RM9000"
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
config CPU_SB1
bool "SB1"
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
endchoice
SiByte Linux port. Seems to give a small performance benefit.
config CPU_HAS_PREFETCH
- bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
- default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000
+ bool
+
+config MIPS_MT
+ bool "Enable MIPS MT"
+
+choice
+ prompt "MIPS MT options"
+ depends on MIPS_MT
+
+config MIPS_MT_SMP
+ bool "Use 1 TC on each available VPE for SMP"
+ select SMP
+
+config MIPS_VPE_LOADER
+ bool "VPE loader support."
+ depends on MIPS_MT
+ help
+ Includes a loader for loading an elf relocatable object
+ onto another VPE and running it.
+
+endchoice
+
+config MIPS_VPE_LOADER_TOM
+ bool "Load VPE program into memory hidden from linux"
+ depends on MIPS_VPE_LOADER
+ default y
+ help
+ The loader can use memory that is present but has been hidden from
+ Linux using the kernel command line option "mem=xxMB". It's up to
+ you to ensure the amount you put in the option and the space your
+ program requires is less or equal to the amount physically present.
-config VTAG_ICACHE
- bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
- default y if CPU_SB1
+# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
+config MIPS_VPE_APSP_API
+ bool "Enable support for AP/SP API (RTLX)"
+ depends on MIPS_VPE_LOADER
config SB1_PASS_1_WORKAROUNDS
bool
config 64BIT_PHYS_ADDR
bool "Support for 64-bit physical address space"
- depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
+ depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
config CPU_ADVANCED
bool "Override CPU Options"
config CPU_HAS_LLDSCD
bool "lld/scd Instructions available" if CPU_ADVANCED
- default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
+ default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
help
Say Y here if your CPU has the lld and scd instructions, the 64-bit
equivalents of ll and sc. Say Y here for better performance, N if
machines which require flushing of write buffers in software. Saying
Y is the safe option; N may result in kernel malfunction and crashes.
+menu "MIPSR2 Interrupt handling"
+ depends on CPU_MIPSR2 && CPU_ADVANCED
+
+config CPU_MIPSR2_IRQ_VI
+ bool "Vectored interrupt mode"
+ help
+ Vectored interrupt mode allowing faster dispatching of interrupts.
+ The board support code needs to be written to take advantage of this
+ mode. Compatibility code is included to allow the kernel to run on
+ a CPU that does not support vectored interrupts. It's safe to
+ say Y here.
+
+config CPU_MIPSR2_IRQ_EI
+ bool "External interrupt controller mode"
+ help
+ Extended interrupt mode takes advantage of an external interrupt
+ controller to allow fast dispatching from many possible interrupt
+ sources. Say N unless you know that external interrupt support is
+ required.
+
+config CPU_MIPSR2_SRS
+ bool "Make shadow set registers available for interrupt handlers"
+ depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
+ help
+ Allow the kernel to use shadow register sets for fast interrupts.
+ Interrupt handlers must be specially written to use shadow sets.
+ Say N unless you know that shadow register set upport is needed.
+endmenu
+
config CPU_HAS_SYNC
bool
depends on !CPU_R3000
default y
+#
+# Use the generic interrupt handling code in kernel/irq/:
+#
+config GENERIC_HARDIRQS
+ bool
+ default y
+
+config GENERIC_IRQ_PROBE
+ bool
+ default y
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
# where it's known to be safe. This will not offer highmem on a few systems
# such as MIPS32 and MIPS64 CPUs which may have virtual and physically
# indexed CPUs but we're playing safe.
-# - We should not offer highmem for system of which we already know that they
-# don't have memory configurations that could gain from highmem support in
-# the kernel because they don't support configurations with RAM at physical
-# addresses > 0x20000000.
+# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
+# know they might have memory configurations that could make use of highmem
+# support.
#
config HIGHMEM
bool "High Memory Support"
- depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX)
+ depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
+
+config CPU_SUPPORTS_HIGHMEM
+ bool
+
+config SYS_SUPPORTS_HIGHMEM
+ bool
config ARCH_FLATMEM_ENABLE
def_bool y
config SMP
bool "Multi-Processing support"
- depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
+ depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
---help---
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
This is purely to save memory - each supported CPU adds
approximately eight kilobytes to the kernel image.
-config PREEMPT
- bool "Preemptible Kernel"
- help
- This option reduces the latency of the kernel when reacting to
- real-time or interactive events by allowing a low priority process to
- be preempted even if it is in kernel mode executing a system call.
- This allows applications to run more reliably even when the system is
- under load.
+source "kernel/Kconfig.preempt"
config RTC_DS1742
bool "DS1742 BRAM/RTC support"
bool
default y if MIPS32_O32 || MIPS32_N32
+config SECCOMP
+ bool "Enable seccomp to safely compute untrusted bytecode"
+ depends on PROC_FS && BROKEN
+ default y
+ help
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via /proc/<pid>/seccomp, it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
+ If unsure, say Y. Only embedded should say N here.
+
config PM
bool "Power Management support (EXPERIMENTAL)"
depends on EXPERIMENTAL && MACH_AU1X00
source "lib/Kconfig"
-#
-# Use the generic interrupt handling code in kernel/irq/:
-#
-config GENERIC_HARDIRQS
- bool
- default y
-
-config GENERIC_IRQ_PROBE
- bool
- default y
-
config ISA_DMA_API
bool
default y
projects / linux-block.git / blobdiff