MIPS: Pistachio: Enable KASLR

[linux-2.6-block.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 68ddb45d6258a3e6401991661566c72249240bf4..7ce55623b5227f949d047fb1c2f4624c4f0737a0 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -399,6 +399,7 @@ config MACH_PISTACHIO
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_MIPS_CPS
        select SYS_SUPPORTS_MULTITHREADING
+       select SYS_SUPPORTS_RELOCATABLE
        select SYS_SUPPORTS_ZBOOT
        select SYS_HAS_EARLY_PRINTK
        select USE_GENERIC_EARLY_PRINTK_8250
@@ -1354,11 +1355,30 @@ config CPU_LOONGSON3
        select CPU_SUPPORTS_HUGEPAGES
        select WEAK_ORDERING
        select WEAK_REORDERING_BEYOND_LLSC
+       select MIPS_PGD_C0_CONTEXT
        select ARCH_REQUIRE_GPIOLIB
        help
                The Loongson 3 processor implements the MIPS64R2 instruction
                set with many extensions.
 
+config LOONGSON3_ENHANCEMENT
+       bool "New Loongson 3 CPU Enhancements"
+       default n
+       select CPU_MIPSR2
+       select CPU_HAS_PREFETCH
+       depends on CPU_LOONGSON3
+       help
+         New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
+         R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
+         FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
+         Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
+         Fast TLB refill support, etc.
+
+         This option enable those enhancements which are not probed at run
+         time. If you want a generic kernel to run on all Loongson 3 machines,
+         please say 'N' here. If you want a high-performance kernel to run on
+         new Loongson 3 machines only, please say 'Y' here.
+
 config CPU_LOONGSON2E
        bool "Loongson 2E"
        depends on SYS_HAS_CPU_LOONGSON2E
@@ -1387,6 +1407,8 @@ config CPU_LOONGSON1B
        bool "Loongson 1B"
        depends on SYS_HAS_CPU_LOONGSON1B
        select CPU_LOONGSON1
+       select ARCH_WANT_OPTIONAL_GPIOLIB
+       select LEDS_GPIO_REGISTER
        help
          The Loongson 1B is a 32-bit SoC, which implements the MIPS32
          release 2 instruction set.
@@ -1685,6 +1707,7 @@ config CPU_XLP
        select CPU_HAS_PREFETCH
        select CPU_MIPSR2
        select CPU_SUPPORTS_HUGEPAGES
+       select MIPS_ASID_BITS_VARIABLE
        help
          Netlogic Microsystems XLP processors.
 endchoice
@@ -1810,6 +1833,7 @@ config CPU_BMIPS4380
        select MIPS_L1_CACHE_SHIFT_6
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU
+       select CPU_HAS_RIXI
 
 config CPU_BMIPS5000
        bool
@@ -1817,10 +1841,12 @@ config CPU_BMIPS5000
        select MIPS_L1_CACHE_SHIFT_7
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU
+       select CPU_HAS_RIXI
 
 config SYS_HAS_CPU_LOONGSON3
        bool
        select CPU_SUPPORTS_CPUFREQ
+       select CPU_HAS_RIXI
 
 config SYS_HAS_CPU_LOONGSON2E
        bool
@@ -1973,11 +1999,15 @@ config CPU_MIPSR1
 config CPU_MIPSR2
        bool
        default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
+       select CPU_HAS_RIXI
        select MIPS_SPRAM
 
 config CPU_MIPSR6
        bool
        default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
+       select CPU_HAS_RIXI
+       select HAVE_ARCH_BITREVERSE
+       select MIPS_ASID_BITS_VARIABLE
        select MIPS_SPRAM
 
 config EVA
@@ -2054,6 +2084,16 @@ config KVM_GUEST_TIMER_FREQ
          emulation when determining guest CPU Frequency. Instead, the guest's
          timer frequency is specified directly.
 
+config MIPS_VA_BITS_48
+       bool "48 bits virtual memory"
+       depends on 64BIT
+       help
+         Support a maximum at least 48 bits of application virtual memory.
+         Default is 40 bits or less, depending on the CPU.
+         This option result in a small memory overhead for page tables.
+         This option is only supported with 16k and 64k page sizes.
+         If unsure, say N.
+
 choice
        prompt "Kernel page size"
        default PAGE_SIZE_4KB
@@ -2061,6 +2101,7 @@ choice
 config PAGE_SIZE_4KB
        bool "4kB"
        depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
+       depends on !MIPS_VA_BITS_48
        help
         This option select the standard 4kB Linux page size.  On some
         R3000-family processors this is the only available page size.  Using
@@ -2070,6 +2111,7 @@ config PAGE_SIZE_4KB
 config PAGE_SIZE_8KB
        bool "8kB"
        depends on CPU_R8000 || CPU_CAVIUM_OCTEON
+       depends on !MIPS_VA_BITS_48
        help
          Using 8kB page size will result in higher performance kernel at
          the price of higher memory consumption.  This option is available
@@ -2088,6 +2130,7 @@ config PAGE_SIZE_16KB
 config PAGE_SIZE_32KB
        bool "32kB"
        depends on CPU_CAVIUM_OCTEON
+       depends on !MIPS_VA_BITS_48
        help
          Using 32kB page size will result in higher performance kernel at
          the price of higher memory consumption.  This option is available
@@ -2383,6 +2426,9 @@ config CPU_HAS_WB
 config XKS01
        bool
 
+config CPU_HAS_RIXI
+       bool
+
 #
 # Vectored interrupt mode is an R2 feature
 #
@@ -2413,6 +2459,21 @@ config CPU_R4000_WORKAROUNDS
 config CPU_R4400_WORKAROUNDS
        bool
 
+config MIPS_ASID_SHIFT
+       int
+       default 6 if CPU_R3000 || CPU_TX39XX
+       default 4 if CPU_R8000
+       default 0
+
+config MIPS_ASID_BITS
+       int
+       default 0 if MIPS_ASID_BITS_VARIABLE
+       default 6 if CPU_R3000 || CPU_TX39XX
+       default 8
+
+config MIPS_ASID_BITS_VARIABLE
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed
@@ -2544,7 +2605,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
-       depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
+       depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
        default y
        help
          Enable hardware performance counter support for perf events. If
@@ -2877,6 +2938,10 @@ choice
 
        config MIPS_CMDLINE_FROM_BOOTLOADER
                bool "Bootloader kernel arguments if available"
+
+       config MIPS_CMDLINE_BUILTIN_EXTEND
+               depends on CMDLINE_BOOL
+               bool "Extend builtin kernel arguments with bootloader arguments"
 endchoice
 
 endmenu