Blackfin: mass clean up of copyright/licensing info

[linux-2.6-block.git] / arch / blackfin / mach-bf561 / secondary.S

diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 35280f06b7b6b0387d475c7921065606e9be4b6a..8e6050369c060b6d83e960492975e98ec0ca2be4 100644 (file)
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -1,26 +1,10 @@
 /*
- * File:         arch/blackfin/mach-bf561/secondary.S
- * Based on:     arch/blackfin/mach-bf561/head.S
- * Author:       Philippe Gerum <rpm@xenomai.org>
+ * BF561 coreB bootstrap file
  *
- *               Copyright 2007 Analog Devices Inc.
+ * Copyright 2007-2009 Analog Devices Inc.
+ *               Philippe Gerum <rpm@xenomai.org>
  *
- * Description:  BF561 coreB bootstrap file
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/linkage.h>
@@ -85,16 +69,10 @@ ENTRY(_coreb_trampoline_start)
        R0 = ~ENICPLB;
        R0 = R0 & R1;
 
-       /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
-       CLI R2;
-       SSYNC;
-#endif
+       /* Disabling of CPLBs should be proceeded by a CSYNC */
+       CSYNC;
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
-       STI R2;
-#endif
 
        /* Turn off the dcache */
        p0.l = LO(DMEM_CONTROL);
@@ -103,16 +81,10 @@ ENTRY(_coreb_trampoline_start)
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
 
-       /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
-       CLI R2;
-       SSYNC;
-#endif
+       /* Disabling of CPLBs should be proceeded by a CSYNC */
+       CSYNC;
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
-       STI R2;
-#endif
 
        /* in case of double faults, save a few things */
        p0.l = _init_retx_coreb;
@@ -126,22 +98,22 @@ ENTRY(_coreb_trampoline_start)
         * below
         */
        GET_PDA(p0, r0);
-       r7 = [p0 + PDA_RETX];
+       r7 = [p0 + PDA_DF_RETX];
        p1.l = _init_saved_retx_coreb;
        p1.h = _init_saved_retx_coreb;
        [p1] = r7;
 
-       r7 = [p0 + PDA_DCPLB];
+       r7 = [p0 + PDA_DF_DCPLB];
        p1.l = _init_saved_dcplb_fault_addr_coreb;
        p1.h = _init_saved_dcplb_fault_addr_coreb;
        [p1] = r7;
 
-       r7 = [p0 + PDA_ICPLB];
+       r7 = [p0 + PDA_DF_ICPLB];
        p1.l = _init_saved_icplb_fault_addr_coreb;
        p1.h = _init_saved_icplb_fault_addr_coreb;
        [p1] = r7;
 
-       r7 = [p0 + PDA_SEQSTAT];
+       r7 = [p0 + PDA_DF_SEQSTAT];
        p1.l = _init_saved_seqstat_coreb;
        p1.h = _init_saved_seqstat_coreb;
        [p1] = r7;