Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3588s.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a3124bd2e092cd5fcb9f5b6ecd1ad089b77afb6b..1576f9bfd6de04ed3324e2d1026bbb070bcb2197 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1185,6 +1185,21 @@
                status = "disabled";
        };
 
+       sdio: mmc@fe2d0000 {
+               compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x00 0xfe2d0000 0x00 0x4000>;
+               interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+                        <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               max-frequency = <200000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdiom1_pins>;
+               power-domains = <&power RK3588_PD_SDIO>;
+               status = "disabled";
+       };
+
        sdhci: mmc@fe2e0000 {
                compatible = "rockchip,rk3588-dwcmshc";
                reg = <0x0 0xfe2e0000 0x0 0x10000>;
@@ -1196,6 +1211,9 @@
                         <&cru TMCLK_EMMC>;
                clock-names = "core", "bus", "axi", "block", "timer";
                max-frequency = <200000000>;
+               pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+                           <&emmc_cmd>, <&emmc_data_strobe>;
+               pinctrl-names = "default";
                resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
                         <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
                         <&cru SRST_T_EMMC>;
@@ -1309,7 +1327,24 @@
                mbi-alias = <0x0 0xfe610000>;
                mbi-ranges = <424 56>;
                msi-controller;
+               ranges;
+               #address-cells = <2>;
                #interrupt-cells = <4>;
+               #size-cells = <2>;
+
+               its0: msi-controller@fe640000 {
+                       compatible = "arm,gic-v3-its";
+                       reg = <0x0 0xfe640000 0x0 0x20000>;
+                       msi-controller;
+                       #msi-cells = <1>;
+               };
+
+               its1: msi-controller@fe660000 {
+                       compatible = "arm,gic-v3-its";
+                       reg = <0x0 0xfe660000 0x0 0x20000>;
+                       msi-controller;
+                       #msi-cells = <1>;
+               };
 
                ppi-partitions {
                        ppi_partition0: interrupt-partition-0 {
@@ -1409,6 +1444,14 @@
                status = "disabled";
        };
 
+       timer0: timer@feae0000 {
+               compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
+               reg = <0x0 0xfeae0000 0x0 0x20>;
+               interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
+               clock-names = "pclk", "timer";
+       };
+
        wdt: watchdog@feaf0000 {
                compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
                reg = <0x0 0xfeaf0000 0x0 0x100>;
@@ -1768,6 +1811,18 @@
                status = "disabled";
        };
 
+       saradc: adc@fec10000 {
+               compatible = "rockchip,rk3588-saradc";
+               reg = <0x0 0xfec10000 0x0 0x10000>;
+               interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+               #io-channel-cells = <1>;
+               clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_P_SARADC>;
+               reset-names = "saradc-apb";
+               status = "disabled";
+       };
+
        i2c6: i2c@fec80000 {
                compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
                reg = <0x0 0xfec80000 0x0 0x1000>;
@@ -1823,6 +1878,60 @@
                status = "disabled";
        };
 
+       otp: efuse@fecc0000 {
+               compatible = "rockchip,rk3588-otp";
+               reg = <0x0 0xfecc0000 0x0 0x400>;
+               clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+                        <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
+               clock-names = "otp", "apb_pclk", "phy", "arb";
+               resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+                        <&cru SRST_OTPC_ARB>;
+               reset-names = "otp", "apb", "arb";
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               cpu_code: cpu-code@2 {
+                       reg = <0x02 0x2>;
+               };
+
+               otp_id: id@7 {
+                       reg = <0x07 0x10>;
+               };
+
+               cpub0_leakage: cpu-leakage@17 {
+                       reg = <0x17 0x1>;
+               };
+
+               cpub1_leakage: cpu-leakage@18 {
+                       reg = <0x18 0x1>;
+               };
+
+               cpul_leakage: cpu-leakage@19 {
+                       reg = <0x19 0x1>;
+               };
+
+               log_leakage: log-leakage@1a {
+                       reg = <0x1a 0x1>;
+               };
+
+               gpu_leakage: gpu-leakage@1b {
+                       reg = <0x1b 0x1>;
+               };
+
+               otp_cpu_version: cpu-version@1c {
+                       reg = <0x1c 0x1>;
+                       bits = <3 3>;
+               };
+
+               npu_leakage: npu-leakage@28 {
+                       reg = <0x28 0x1>;
+               };
+
+               codec_leakage: codec-leakage@29 {
+                       reg = <0x29 0x1>;
+               };
+       };
+
        dmac2: dma-controller@fed10000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xfed10000 0x0 0x4000>;