Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

[linux-2.6-block.git] / arch / arm / mm / cache-v7.S

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 8c83b458688323c6730e65668fe0bb046aaca9ac..0ee8fc4b4672c6d2123c231a47b61cb870ec6052 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -16,6 +16,14 @@
 
 #include "proc-macros.S"
 
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif
 /*
  * The secondary kernel init calls v7_flush_dcache_all before it enables
  * the L1; however, the L1 comes out of reset in an undefined state, so
@@ -160,6 +168,9 @@ loop2:
 skip:
        add     r10, r10, #2                    @ increment cache number
        cmp     r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+       dsb
+#endif
        bgt     flush_levels
 finished:
        mov     r10, #0                         @ switch back to cache level 0
@@ -281,7 +292,12 @@ ENTRY(v7_coherent_user_range)
        cmp     r12, r1
        blo     1b
        dsb     ishst
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+       ldr     r3, =icache_size
+       ldr     r2, [r3, #0]
+#else
        icache_line_size r2, r3
+#endif
        sub     r3, r2, #1
        bic     r12, r0, r3
 2: