treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

[linux-block.git] / arch / arm / mach-tegra / sleep-tegra30.S

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d0b4c486ddbfaa1067d366c375675835910a1750..b408fa56eb892dae07672ca16c6b03bd7cdb11ab 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/linkage.h>
@@ -44,8 +33,6 @@
 #define EMC_XM2VTTGENPADCTRL           0x310
 #define EMC_XM2VTTGENPADCTRL2          0x314
 
-#define MC_EMEM_ARB_CFG                        0x90
-
 #define PMC_CTRL                       0x0
 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
 
@@ -420,22 +407,6 @@ _pll_m_c_x_done:
        movweq  r0, #:lower16:TEGRA124_EMC_BASE
        movteq  r0, #:upper16:TEGRA124_EMC_BASE
 
-       cmp     r10, #TEGRA30
-       moveq   r2, #0x20
-       movweq  r4, #:lower16:TEGRA_MC_BASE
-       movteq  r4, #:upper16:TEGRA_MC_BASE
-       cmp     r10, #TEGRA114
-       moveq   r2, #0x34
-       movweq  r4, #:lower16:TEGRA114_MC_BASE
-       movteq  r4, #:upper16:TEGRA114_MC_BASE
-       cmp     r10, #TEGRA124
-       moveq   r2, #0x20
-       movweq  r4, #:lower16:TEGRA124_MC_BASE
-       movteq  r4, #:upper16:TEGRA124_MC_BASE
-
-       ldr     r1, [r5, r2]            @ restore MC_EMEM_ARB_CFG
-       str     r1, [r4, #MC_EMEM_ARB_CFG]
-
 exit_self_refresh:
        ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
        str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -564,7 +535,6 @@ tegra30_sdram_pad_address:
        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
-       .word   TEGRA_MC_BASE + MC_EMEM_ARB_CFG                         @0x20
 tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
@@ -581,7 +551,6 @@ tegra114_sdram_pad_address:
        .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
-       .word   TEGRA114_MC_BASE + MC_EMEM_ARB_CFG                      @0x34
 tegra114_sdram_pad_adress_end:
 
 tegra124_sdram_pad_address:
@@ -593,7 +562,6 @@ tegra124_sdram_pad_address:
        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
-       .word   TEGRA124_MC_BASE + MC_EMEM_ARB_CFG                      @0x20
 tegra124_sdram_pad_address_end:
 
 tegra30_sdram_pad_size: