[ARM] Kirkwood: platform device registration for the crypto engine

[linux-block.git] / arch / arm / mach-kirkwood / include / mach / kirkwood.h

diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 38c9868535902c3f984621a80a123392b9127048..07af858814a0dc418b0d50e68293d1d82ca2d4b9 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -20,16 +20,18 @@
  * f1000000    on-chip peripheral registers
  * f2000000    PCIe I/O space
  * f3000000    NAND controller address window
+ * f4000000    Security Accelerator SRAM
  *
  * virt                phys            size
  * fee00000    f1000000        1M      on-chip peripheral registers
  * fef00000    f2000000        1M      PCIe I/O space
  */
 
+#define KIRKWOOD_SRAM_PHYS_BASE                0xf4000000
+#define KIRKWOOD_SRAM_SIZE             SZ_2K
+
 #define KIRKWOOD_NAND_MEM_PHYS_BASE    0xf3000000
-#define KIRKWOOD_NAND_MEM_SIZE         SZ_64K /* 1K is sufficient, but 64K
-                                               * is the minimal window size
-                                               */
+#define KIRKWOOD_NAND_MEM_SIZE         SZ_1K
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE     0xf2000000
 #define KIRKWOOD_PCIE_IO_VIRT_BASE     0xfef00000
@@ -43,49 +45,12 @@
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE    0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE         SZ_128M
 
-/*
- * MBUS bridge registers.
- */
-#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
-#define   CPU_RESET            0x00000002
-#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN    0x00000004
-#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET           0x00000001
-#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0    0x0002
-#define   BRIDGE_INT_TIMER1    0x0004
-#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
-#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_LOW_OFF    0x0000
-#define   IRQ_MASK_LOW_OFF     0x0004
-#define   IRQ_CAUSE_HIGH_OFF   0x0010
-#define   IRQ_MASK_HIGH_OFF    0x0014
-#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
-#define  L2_CONFIG_REG         (BRIDGE_VIRT_BASE | 0x0128)
-#define   L2_WRITETHROUGH      0x00000010
-
-/*
- * Supported devices and revisions.
- */
-#define MV88F6281_DEV_ID       0x6281
-#define MV88F6281_REV_Z0       0
-#define MV88F6281_REV_A0       2
-
-#define MV88F6192_DEV_ID       0x6192
-#define MV88F6192_REV_Z0       0
-#define MV88F6192_REV_A0       2
-
-#define MV88F6180_DEV_ID       0x6180
-#define MV88F6180_REV_A0       2
-
 /*
  * Register Map
  */
 #define DDR_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
 #define  DDR_WINDOW_CPU_BASE   (DDR_VIRT_BASE | 0x1500)
+#define DDR_OPERATION_BASE     (DDR_VIRT_BASE | 0x1418)
 
 #define DEV_BUS_PHYS_BASE      (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
 #define DEV_BUS_VIRT_BASE      (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
@@ -99,7 +64,13 @@
 #define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
 #define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
 
+#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+
+#define CRYPTO_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
+
 #define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+#define PCIE_LINK_CTRL         (PCIE_VIRT_BASE | 0x70)
+#define PCIE_STATUS            (PCIE_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
@@ -116,8 +87,26 @@
 #define GE01_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
 
 #define SATA_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+#define SATA_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
+#define SATA0_IF_CTRL          (SATA_VIRT_BASE | 0x2050)
+#define SATA0_PHY_MODE_2       (SATA_VIRT_BASE | 0x2330)
+#define SATA1_IF_CTRL          (SATA_VIRT_BASE | 0x4050)
+#define SATA1_PHY_MODE_2       (SATA_VIRT_BASE | 0x4330)
 
 #define SDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
 
+/*
+ * Supported devices and revisions.
+ */
+#define MV88F6281_DEV_ID       0x6281
+#define MV88F6281_REV_Z0       0
+#define MV88F6281_REV_A0       2
+
+#define MV88F6192_DEV_ID       0x6192
+#define MV88F6192_REV_Z0       0
+#define MV88F6192_REV_A0       2
+
+#define MV88F6180_DEV_ID       0x6180
+#define MV88F6180_REV_A0       2
 
 #endif