ARM: imx: add L2 page power control for GPC

[linux-2.6-block.git] / arch / arm / mach-imx / gpc.c

diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index de535cb679b36d58d6cb88106656e1e260c490c0..e11159d40fb8166adf43573d211e264ab2f45ca2 100644 (file)
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -20,6 +20,7 @@
 #include "common.h"
 #include "hardware.h"
 
+#define GPC_CNTR               0x0
 #define GPC_IMR1               0x008
 #define GPC_PGC_CPU_PDN                0x2a0
 #define GPC_PGC_CPU_PUPSCR     0x2a4
@@ -27,6 +28,8 @@
 #define GPC_PGC_SW2ISO_SHIFT   0x8
 #define GPC_PGC_SW_SHIFT       0x0
 
+#define GPC_CNTR_L2_PGE_SHIFT  22
+
 #define IMR_NUM                        4
 #define GPC_MAX_IRQS           (IMR_NUM * 32)
 
@@ -51,6 +54,17 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off)
        writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
 }
 
+void imx_gpc_set_l2_mem_power_in_lpm(bool power_off)
+{
+       u32 val;
+
+       val = readl_relaxed(gpc_base + GPC_CNTR);
+       val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT);
+       if (power_off)
+               val |= 1 << GPC_CNTR_L2_PGE_SHIFT;
+       writel_relaxed(val, gpc_base + GPC_CNTR);
+}
+
 void imx_gpc_pre_suspend(bool arm_power_off)
 {
        void __iomem *reg_imr1 = gpc_base + GPC_IMR1;