Merge tag 'docs-5.3' of git://git.lwn.net/linux

[linux-2.6-block.git] / arch / arm / Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 249d788f312418f16f21813f8220f8217565744b..ad00e17d6988ee11ef9b224c595860d9a7f8f644 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1175,6 +1175,14 @@ config ARM_ERRATA_825619
          DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
          and Device/Strongly-Ordered loads and stores might cause deadlock
 
+config ARM_ERRATA_857271
+       bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 857271 Cortex-A12
+         (all revs) erratum. Under very rare timing conditions, the CPU might
+         hang. The workaround is expected to have a < 1% performance impact.
+
 config ARM_ERRATA_852421
        bool "ARM errata: A17: DMB ST might fail to create order between stores"
        depends on CPU_V7
@@ -1196,6 +1204,16 @@ config ARM_ERRATA_852423
          config option from the A12 erratum due to the way errata are checked
          for and handled.
 
+config ARM_ERRATA_857272
+       bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 857272 Cortex-A17 erratum.
+         This erratum is not known to be fixed in any A17 revision.
+         This is identical to Cortex-A12 erratum 857271.  It is a separate
+         config option from the A12 erratum due to the way errata are checked
+         for and handled.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1232,6 +1250,18 @@ config PCI_HOST_ITE8152
        default y
        select DMABOUNCE
 
+config ARM_ERRATA_814220
+       bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+       depends on CPU_V7
+       help
+         The v7 ARM states that all cache and branch predictor maintenance
+         operations that do not specify an address execute, relative to
+         each other, in program order.
+         However, because of this erratum, an L2 set/way cache maintenance
+         operation can overtake an L1 set/way cache maintenance operation.
+         This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
+         r0p4, r0p5.
+
 endmenu
 
 menu "Kernel Features"